2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <southbridge/amd/sb700/sb700.h>
31 #define ADT7461_ADDRESS 0x4C
32 #define ARA_ADDRESS 0x0C /* Alert Response Address */
34 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
35 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
38 #define ADT7461_read_byte(address) \
39 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
40 #define ARA_read_byte(address) \
41 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
42 #define ADT7461_write_byte(address, val) \
43 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
45 #define SMBUS_IO_BASE 0x6000
47 uint64_t uma_memory_base, uma_memory_size;
49 void set_pcie_dereset(void);
50 void set_pcie_reset(void);
51 int is_dev3_present(void);
53 void set_pcie_dereset()
58 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
59 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
60 byte = pm_ioread(0x8d);
61 byte &= ~((1 << 1) | (1 << 2));
62 pm_iowrite(0x8d, byte);
64 /* set the GPM8 and GPM9 output enable and the value to 1 */
65 byte = pm_ioread(0x94);
66 byte &= ~((1 << 2) | (1 << 3));
67 byte |= ((1 << 0) | (1 << 1));
68 pm_iowrite(0x94, byte);
70 /* set the GPIO65 output enable and the value is 1 */
71 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
72 word = pci_read_config16(sm_dev, 0x7e);
75 pci_write_config16(sm_dev, 0x7e, word);
84 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
85 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
86 byte = pm_ioread(0x8d);
87 byte &= ~((1 << 1) | (1 << 2));
88 pm_iowrite(0x8d, byte);
90 /* set the GPM8 and GPM9 output enable and the value to 0 */
91 byte = pm_ioread(0x94);
92 byte &= ~((1 << 2) | (1 << 3));
93 byte &= ~((1 << 0) | (1 << 1));
94 pm_iowrite(0x94, byte);
96 /* set the GPIO65 output enable and the value is 0 */
97 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
98 word = pci_read_config16(sm_dev, 0x7e);
101 pci_write_config16(sm_dev, 0x7e, word);
107 * justify the dev3 is exist or not
109 int is_dev3_present(void)
114 /* access the smbus extended register */
115 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
117 /* put the GPIO68 output to tristate */
118 word = pci_read_config16(sm_dev, 0x7e);
120 pci_write_config16(sm_dev, 0x7e,word);
122 /* read the GPIO68 input status */
123 word = pci_read_config16(sm_dev, 0x7e);
125 if(word & (1 << 10)){
138 static void set_gpio40_gfx(void)
144 /* disable the GPIO40 as CLKREQ2# function */
145 byte = pm_ioread(0xd3);
147 pm_iowrite(0xd3, byte);
149 /* disable the GPIO40 as CLKREQ3# function */
150 byte = pm_ioread(0xd4);
152 pm_iowrite(0xd4, byte);
154 /* enable pull up for GPIO68 */
155 byte = pm2_ioread(0xf1);
157 pm2_iowrite(0xf1, byte);
159 /* access the smbus extended register */
160 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
162 /*if the dev3 is present, set the gfx to 2x8 lanes*/
163 /*otherwise set the gfx to 1x16 lanes*/
164 if(is_dev3_present()){
166 printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
167 /* when the gpio40 is configured as GPIO, this will enable the output */
168 pci_write_config32(sm_dev, 0xf8, 0x4);
169 dword = pci_read_config32(sm_dev, 0xfc);
172 /* When the gpio40 is configured as GPIO, this will represent the output value*/
173 /* 1 :enable two x8 , 0 : master slot enable only */
175 pci_write_config32(sm_dev, 0xfc, dword);
178 printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
179 /* when the gpio40 is configured as GPIO, this will enable the output */
180 pci_write_config32(sm_dev, 0xf8, 0x4);
181 dword = pci_read_config32(sm_dev, 0xfc);
184 /* When the gpio40 is configured as GPIO, this will represent the output value*/
185 /* 1 :enable two x8 , 0 : master slot enable only */
187 pci_write_config32(sm_dev, 0xfc, dword);
194 static void set_thermal_config(void)
201 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
202 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
203 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
204 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
206 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
207 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
209 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
210 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
211 printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
213 /* sb700 settings for thermal config */
214 /* set SB700 GPIO 64 to GPIO with pull-up */
215 byte = pm2_ioread(0x42);
217 pm2_iowrite(0x42, byte);
219 /* set GPIO 64 to input */
220 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
221 word = pci_read_config16(sm_dev, 0x56);
223 pci_write_config16(sm_dev, 0x56, word);
225 /* set GPIO 64 internal pull-up */
226 byte = pm2_ioread(0xf0);
228 pm2_iowrite(0xf0, byte);
230 /* set Talert to be active low */
231 byte = pm_ioread(0x67);
233 pm_iowrite(0x67, byte);
235 /* set Talert to generate ACPI event */
236 byte = pm_ioread(0x3c);
238 pm_iowrite(0x3c, byte);
241 /* byte = pm_ioread(0x68);
243 * pm_iowrite(0x68, byte);
245 * byte = pm_ioread(0x55);
247 * pm_iowrite(0x55, byte);
249 * byte = pm_ioread(0x67);
250 * byte &= ~( 1 << 6);
251 * pm_iowrite(0x67, byte);
255 /*************************************************
256 * enable the dedicated function in ma785gmt board.
257 * This function called early than rs780_enable.
258 *************************************************/
259 static void ma785gmt_enable(device_t dev)
261 printk(BIOS_INFO, "Mainboard Gigabyte ma785gmt Enable. dev=0x%p\n", dev);
263 #if (CONFIG_GFXUMA == 1)
266 /* TOP_MEM: the top of DRAM below 4G */
267 msr = rdmsr(TOP_MEM);
269 "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
270 __func__, msr.lo, msr.hi);
272 /* TOP_MEM2: the top of DRAM above 4G */
273 msr2 = rdmsr(TOP_MEM2);
275 "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
276 __func__, msr2.lo, msr2.hi);
279 case 0x10000000: /* 256M system memory */
280 uma_memory_size = 0x4000000; /* 64M recommended UMA */
283 case 0x20000000: /* 512M system memory */
284 uma_memory_size = 0x8000000; /* 128M recommended UMA */
287 default: /* 1GB and above system memory */
288 uma_memory_size = 0x10000000; /* 256M recommended UMA */
292 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
293 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
294 __func__, uma_memory_size, uma_memory_base);
298 uma_memory_size = 0x8000000; /* 128M recommended UMA */
299 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
303 /* get_ide_dma66(); */
304 set_thermal_config();
308 int add_mainboard_resources(struct lb_memory *mem)
310 /* UMA is removed from system memory in the northbridge code, but
311 * in some circumstances we want the memory mentioned as reserved.
313 #if (CONFIG_GFXUMA == 1)
314 printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
315 uma_memory_base, uma_memory_size);
316 lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
322 struct chip_operations mainboard_ops = {
323 CHIP_NAME("GIGABYTE MA785GMT Mainboard")
324 .enable_dev = ma785gmt_enable,