2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define RAMINIT_SYSINFO 1
24 #define K8_ALLOCATE_IO_RANGE 1
26 #define QRANK_DIMM_SUPPORT 1
28 #if CONFIG_LOGICAL_CPUS==1
29 #define SET_NB_CFG_54 1
32 //used by init_cpus and fidvid
34 //if we want to wait for core1 done before DQS training, set it to 0
35 #define SET_FIDVID_CORE0_ONLY 1
37 #if CONFIG_K8_REV_F_SUPPORT == 1
38 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
43 #include <device/pci_def.h>
44 #include <device/pci_ids.h>
46 #include <device/pnp_def.h>
47 #include <arch/romcc_io.h>
48 #include <cpu/x86/lapic.h>
49 #include <pc80/mc146818rtc.h>
51 #include <console/console.h>
53 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
54 #include "pc80/usbdebug_serial.c"
56 #include "lib/ramtest.c"
58 #include <cpu/amd/model_fxx_rev.h>
60 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
61 #include "northbridge/amd/amdk8/raminit.h"
62 #include "cpu/amd/model_fxx/apic_timer.c"
63 #include "lib/delay.c"
65 #include "cpu/x86/lapic/boot_cpu.c"
66 #include "northbridge/amd/amdk8/reset_test.c"
67 #include "superio/ite/it8716f/it8716f_early_serial.c"
68 #include "superio/ite/it8716f/it8716f_early_init.c"
70 #include "cpu/x86/bist.h"
72 #include "northbridge/amd/amdk8/debug.c"
74 #include "cpu/x86/mtrr/earlymtrr.c"
76 #include "northbridge/amd/amdk8/setup_resource_map.c"
78 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
79 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
81 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
83 static void memreset(int controllers, const struct mem_controller *ctrl)
87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
92 static inline int spd_read_byte(unsigned device, unsigned address)
94 return smbus_read_byte(device, address);
98 #define MCP55_USE_NIC 1
99 #define MCP55_USE_AZA 1
101 #define MCP55_PCI_E_X_0 0
103 #define MCP55_MB_SETUP \
104 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
105 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
106 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
107 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
108 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
109 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
111 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
112 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
116 #include "northbridge/amd/amdk8/amdk8_f.h"
117 #include "northbridge/amd/amdk8/incoherent_ht.c"
118 #include "northbridge/amd/amdk8/coherent_ht.c"
119 #include "northbridge/amd/amdk8/raminit_f.c"
120 #include "lib/generic_sdram.c"
122 #include "resourcemap.c"
124 #include "cpu/amd/dualcore/dualcore.c"
126 #include "cpu/amd/car/post_cache_as_ram.c"
128 #include "cpu/amd/model_fxx/init_cpus.c"
130 #include "cpu/amd/model_fxx/fidvid.c"
132 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
133 #include "northbridge/amd/amdk8/early_ht.c"
135 static void sio_setup(void)
140 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
142 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
144 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
146 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
148 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
150 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
153 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
155 static const uint16_t spd_addr [] = {
157 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
158 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
160 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
161 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
164 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
165 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
168 unsigned bsp_apicid = 0;
171 if (!cpu_init_detectedx && boot_cpu()) {
172 /* Nothing special needs to be done to find bus 0 */
173 /* Allow the HT devices to be found */
175 enumerate_ht_chain();
179 /* Setup the mcp55 */
184 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
187 pnp_enter_ext_func_mode(SERIAL_DEV);
188 /* The following line will set CLKIN to 24 MHz, external */
189 pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
190 tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
191 /* Is serial flash enabled? Then enable writing to serial flash. */
193 pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
194 pnp_set_logical_device(GPIO_DEV);
195 /* Set Serial Flash interface to 0x0820 */
196 pnp_write_config(GPIO_DEV, 0x64, 0x08);
197 pnp_write_config(GPIO_DEV, 0x65, 0x20);
198 /* We can get away with not resetting the logical device because
199 * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
202 it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
203 pnp_exit_ext_func_mode(SERIAL_DEV);
205 setup_mb_resource_map();
209 /* Halt if there was a built in self test failure */
210 report_bist_failure(bist);
213 mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
214 early_usbdebug_init();
217 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
219 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
221 #if CONFIG_MEM_TRAIN_SEQ == 1
222 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
224 setup_coherent_ht_domain(); // routing table and start other core0
226 wait_all_core0_started();
227 #if CONFIG_LOGICAL_CPUS==1
228 // It is said that we should start core1 after all core0 launched
229 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
230 * So here need to make sure last core0 is started, esp for two way system,
231 * (there may be apic id conflicts in that case)
234 wait_all_other_cores_started(bsp_apicid);
237 /* it will set up chains and store link pair for optimization later */
238 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
244 msr=rdmsr(0xc0010042);
245 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
251 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
253 init_fidvid_bsp(bsp_apicid);
255 // show final fid and vid
258 msr=rdmsr(0xc0010042);
259 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
264 init_timer(); // Need to use TMICT to synconize FID/VID
266 needs_reset |= optimize_link_coherent_ht();
267 needs_reset |= optimize_link_incoherent_ht(sysinfo);
268 needs_reset |= mcp55_early_setup_x();
270 // fidvid change will issue one LDTSTOP and the HT change will be effective too
272 print_info("ht reset -\n");
275 allow_all_aps_stop(bsp_apicid);
277 //It's the time to set ctrl in sysinfo now;
278 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
282 /* all ap stopped? */
284 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
286 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now