2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <console/console.h>
24 #include <arch/smp/mpspec.h>
25 #include <device/pci.h>
29 #include <cpu/amd/amdk8_sysconf.h>
30 extern unsigned char bus_isa;
31 extern unsigned char bus_mcp55[8]; //1
33 extern unsigned apicid_mcp55;
35 extern unsigned bus_type[256];
39 static void *smp_write_config_table(void *v)
41 static const char sig[4] = "PCMP";
42 static const char oem[8] = "COREBOOT";
43 static const char productid[12] = "M57SLI ";
44 struct mp_config_table *mc;
49 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
50 memset(mc, 0, sizeof(*mc));
52 memcpy(mc->mpc_signature, sig, sizeof(sig));
53 mc->mpc_length = sizeof(*mc); /* initially just the header */
55 mc->mpc_checksum = 0; /* not yet computed */
56 memcpy(mc->mpc_oem, oem, sizeof(oem));
57 memcpy(mc->mpc_productid, productid, sizeof(productid));
60 mc->mpc_entry_count = 0; /* No entries yet... */
61 mc->mpc_lapic = LAPIC_ADDR;
66 smp_write_processors(mc);
72 /* define bus and isa numbers */
73 for(j= 0; j < 256 ; j++) {
75 smp_write_bus(mc, j, "PCI ");
77 smp_write_bus(mc, bus_isa, "ISA ");
79 /*I/O APICs: APIC ID Version State Address*/
84 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
86 res = find_resource(dev, PCI_BASE_ADDRESS_1);
88 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
90 /* set up the interrupt registers of mcp55 */
91 pci_write_config32(dev, 0x7c, 0xc643c643);
92 pci_write_config32(dev, 0x80, 0x8da01009);
93 pci_write_config32(dev, 0x84, 0x200018d2);
97 /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
98 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
100 /* ISA ints are edge-triggered, and usually originate from the ISA bus,
103 #define ISA_INT(intr, pin)\
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_mcp55, (pin))
118 /* PCI interrupts are level triggered, and are
119 * associated with a specific bus/device/function tuple.
121 #define PCI_INT(bus, dev, fn, pin) \
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
123 bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
125 PCI_INT(0,sbdn+1,1, 10); /* SMBus */
126 PCI_INT(0,sbdn+2,0, 22); /* USB */
127 PCI_INT(0,sbdn+2,1, 23); /* USB */
128 PCI_INT(0,sbdn+4,0, 21); /* IDE */
129 PCI_INT(0,sbdn+5,0, 20); /* SATA */
130 PCI_INT(0,sbdn+5,1, 21); /* SATA */
131 PCI_INT(0,sbdn+5,2, 22); /* SATA */
132 PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
133 PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
135 /* The PCIe slots, each on its own bus */
140 PCI_INT(j,0,i, 16+k);
146 /* On bus 1: the PCI bus slots...
147 pyhsical PCI slots are j = 7,8
154 PCI_INT(1,j,i, 16+k);
159 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
160 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
161 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
162 /* There is no extension information... */
164 /* Compute the checksums */
165 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
166 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
167 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
168 mc, smp_next_mpe_entry(mc));
169 return smp_next_mpe_entry(mc);
172 unsigned long write_smp_table(unsigned long addr)
175 v = smp_write_floating_table(addr);
176 return (unsigned long)smp_write_config_table(v);