2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define K8_ALLOCATE_IO_RANGE 1
28 //#define K8_SCAN_PCI_BUS 1
31 #define QRANK_DIMM_SUPPORT 1
33 #if CONFIG_LOGICAL_CPUS==1
34 #define SET_NB_CFG_54 1
37 //used by init_cpus and fidvid
38 #define K8_SET_FIDVID 1
39 //if we want to wait for core1 done before DQS training, set it to 0
40 #define K8_SET_FIDVID_CORE0_ONLY 1
42 #if K8_REV_F_SUPPORT == 1
43 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
46 #define DBGP_DEFAULT 7
49 #include <device/pci_def.h>
50 #include <device/pci_ids.h>
52 #include <device/pnp_def.h>
53 #include <arch/romcc_io.h>
54 #include <cpu/x86/lapic.h>
55 #include "option_table.h"
56 #include "pc80/mc146818rtc_early.c"
58 #if USE_FAILOVER_IMAGE==0
59 #include "pc80/serial.c"
60 #include "arch/i386/lib/console.c"
61 #if CONFIG_USBDEBUG_DIRECT
62 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
63 #include "pc80/usbdebug_direct_serial.c"
65 #include "ram/ramtest.c"
67 #include <cpu/amd/model_fxx_rev.h>
69 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
70 #include "northbridge/amd/amdk8/raminit.h"
71 #include "cpu/amd/model_fxx/apic_timer.c"
72 #include "lib/delay.c"
76 #include "cpu/x86/lapic/boot_cpu.c"
77 #include "northbridge/amd/amdk8/reset_test.c"
78 #include "superio/ite/it8716f/it8716f_early_serial.c"
79 #include "superio/ite/it8716f/it8716f_early_init.c"
81 #if USE_FAILOVER_IMAGE==0
83 #include "cpu/x86/bist.h"
85 #if CONFIG_USE_INIT == 0
86 #include "lib/memcpy.c"
89 #include "northbridge/amd/amdk8/debug.c"
91 #include "cpu/amd/mtrr/amd_earlymtrr.c"
93 #include "northbridge/amd/amdk8/setup_resource_map.c"
95 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
96 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
98 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
100 static void memreset_setup(void)
104 static void memreset(int controllers, const struct mem_controller *ctrl)
108 static inline void activate_spd_rom(const struct mem_controller *ctrl)
113 static inline int spd_read_byte(unsigned device, unsigned address)
115 return smbus_read_byte(device, address);
118 #include "northbridge/amd/amdk8/amdk8_f.h"
119 #include "northbridge/amd/amdk8/coherent_ht.c"
121 #include "northbridge/amd/amdk8/incoherent_ht.c"
123 #include "northbridge/amd/amdk8/raminit_f.c"
125 #include "sdram/generic_sdram.c"
127 #include "resourcemap.c"
129 #include "cpu/amd/dualcore/dualcore.c"
132 #define MCP55_USE_NIC 1
133 #define MCP55_USE_AZA 1
135 #define MCP55_PCI_E_X_0 0
137 #define MCP55_MB_SETUP \
138 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
139 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
140 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
141 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
142 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
143 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
145 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
146 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
148 #include "cpu/amd/car/copy_and_run.c"
150 #include "cpu/amd/car/post_cache_as_ram.c"
152 #include "cpu/amd/model_fxx/init_cpus.c"
154 #include "cpu/amd/model_fxx/fidvid.c"
158 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
160 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
161 #include "northbridge/amd/amdk8/early_ht.c"
164 static void sio_setup(void)
171 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
173 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
175 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
177 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
179 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
181 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
184 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
186 unsigned last_boot_normal_x = last_boot_normal();
188 /* Is this a cpu only reset? or Is this a secondary cpu? */
189 if ((cpu_init_detectedx) || (!boot_cpu())) {
190 if (last_boot_normal_x) {
197 /* Nothing special needs to be done to find bus 0 */
198 /* Allow the HT devices to be found */
200 enumerate_ht_chain();
204 /* Setup the mcp55 */
207 /* Is this a deliberate reset by the bios */
208 if (bios_reset_detected() && last_boot_normal_x) {
211 /* This is the primary cpu how should I boot? */
212 else if (do_normal_boot()) {
219 __asm__ volatile ("jmp __normal_image"
221 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
225 #if HAVE_FAILOVER_BOOT==1
226 __asm__ volatile ("jmp __fallback_image"
228 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
234 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
236 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
238 #if HAVE_FAILOVER_BOOT==1
239 #if USE_FAILOVER_IMAGE==1
240 failover_process(bist, cpu_init_detectedx);
242 real_main(bist, cpu_init_detectedx);
245 #if USE_FALLBACK_IMAGE == 1
246 failover_process(bist, cpu_init_detectedx);
248 real_main(bist, cpu_init_detectedx);
252 #if USE_FAILOVER_IMAGE==0
254 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
256 static const uint16_t spd_addr [] = {
257 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
258 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
259 #if CONFIG_MAX_PHYSICAL_CPUS > 1
260 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
261 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
265 struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
268 unsigned bsp_apicid = 0;
272 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
275 pnp_enter_ext_func_mode(SERIAL_DEV);
276 /* The following line will set CLKIN to 24 MHz, external */
277 pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
278 tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
279 /* Is serial flash enabled? Then enable writing to serial flash. */
281 pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
282 pnp_set_logical_device(GPIO_DEV);
283 /* Set Serial Flash interface to 0x0820 */
284 pnp_write_config(GPIO_DEV, 0x64, 0x08);
285 pnp_write_config(GPIO_DEV, 0x65, 0x20);
286 /* We can get away with not resetting the logical device because
287 * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that.
290 it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
291 pnp_exit_ext_func_mode(SERIAL_DEV);
293 setup_mb_resource_map();
297 /* Halt if there was a built in self test failure */
298 report_bist_failure(bist);
301 #if CONFIG_USBDEBUG_DIRECT
302 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
303 early_usbdebug_direct_init();
306 print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
308 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
310 #if MEM_TRAIN_SEQ == 1
311 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
313 setup_coherent_ht_domain(); // routing table and start other core0
315 wait_all_core0_started();
316 #if CONFIG_LOGICAL_CPUS==1
317 // It is said that we should start core1 after all core0 launched
318 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
319 * So here need to make sure last core0 is started, esp for two way system,
320 * (there may be apic id conflicts in that case)
323 wait_all_other_cores_started(bsp_apicid);
326 /* it will set up chains and store link pair for optimization later */
327 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
329 #if K8_SET_FIDVID == 1
333 msr=rdmsr(0xc0010042);
334 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
340 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
342 init_fidvid_bsp(bsp_apicid);
344 // show final fid and vid
347 msr=rdmsr(0xc0010042);
348 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
353 needs_reset |= optimize_link_coherent_ht();
354 needs_reset |= optimize_link_incoherent_ht(sysinfo);
355 needs_reset |= mcp55_early_setup_x();
357 // fidvid change will issue one LDTSTOP and the HT change will be effective too
359 print_info("ht reset -\r\n");
362 allow_all_aps_stop(bsp_apicid);
364 //It's the time to set ctrl in sysinfo now;
365 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
371 //do we need apci timer, tsc...., only debug need it for better output
372 /* all ap stopped? */
373 // init_timer(); // Need to use TMICT to synconize FID/VID
375 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
377 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now