2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 ## XIP_ROM_SIZE must be a power of 2.
23 default XIP_ROM_SIZE = 64 * 1024
24 include /config/failovercalculation.lb
29 ## Build the objects we have code for in this directory.
33 #needed by irq_tables and mptable and acpi_tables
36 if HAVE_MP_TABLE object mptable.o end
37 if HAVE_PIRQ_TABLE object irq_tables.o end
41 makerule ./cache_as_ram_auto.o
42 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
43 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
46 makerule ./cache_as_ram_auto.inc
47 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
48 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
49 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
50 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
56 if CONFIG_AP_CODE_IN_CAR
58 depends "$(MAINBOARD)/apc_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
61 ldscript /arch/i386/init/ldscript_apc.lb
67 ## Build our 16 bit and 32 bit coreboot entry code
71 mainboardinit cpu/x86/16bit/entry16.inc
72 ldscript /cpu/x86/16bit/entry16.lds
76 mainboardinit cpu/x86/16bit/entry16.inc
77 ldscript /cpu/x86/16bit/entry16.lds
81 mainboardinit cpu/x86/32bit/entry32.inc
84 ldscript /cpu/x86/32bit/entry32.lds
88 ldscript /cpu/amd/car/cache_as_ram.lds
92 ## Build our reset vector (This is where coreboot is entered)
96 mainboardinit cpu/x86/16bit/reset16.inc
97 ldscript /cpu/x86/16bit/reset16.lds
99 mainboardinit cpu/x86/32bit/reset32.inc
100 ldscript /cpu/x86/32bit/reset32.lds
103 if USE_FALLBACK_IMAGE
104 mainboardinit cpu/x86/16bit/reset16.inc
105 ldscript /cpu/x86/16bit/reset16.lds
107 mainboardinit cpu/x86/32bit/reset32.inc
108 ldscript /cpu/x86/32bit/reset32.lds
113 ## Include an id string (For safe flashing)
115 mainboardinit southbridge/nvidia/mcp55/id.inc
116 ldscript /southbridge/nvidia/mcp55/id.lds
119 ## ROMSTRAP table for MCP55
121 if HAVE_FAILOVER_BOOT
122 if USE_FAILOVER_IMAGE
123 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
124 ldscript /southbridge/nvidia/mcp55/romstrap.lds
127 if USE_FALLBACK_IMAGE
128 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
129 ldscript /southbridge/nvidia/mcp55/romstrap.lds
134 ## Setup Cache-As-Ram
136 mainboardinit cpu/amd/car/cache_as_ram.inc
139 ### This is the early phase of coreboot startup
140 ### Things are delicate and we test to see if we should
141 ### failover to another image.
143 if HAVE_FAILOVER_BOOT
144 if USE_FAILOVER_IMAGE
145 ldscript /arch/i386/lib/failover_failover.lds
148 if USE_FALLBACK_IMAGE
149 ldscript /arch/i386/lib/failover.lds
161 initobject cache_as_ram_auto.o
163 mainboardinit ./cache_as_ram_auto.inc
167 ## Include the secondary Configuration files
171 chip northbridge/amd/amdk8/root_complex
172 device apic_cluster 0 on
173 chip cpu/amd/socket_AM2
177 device pci_domain 0 on
178 chip northbridge/amd/amdk8 #mc0
180 # devices on link 0, link 0 == LDT 0
181 chip southbridge/nvidia/mcp55
182 device pci 0.0 on end # HT
183 device pci 1.0 on # LPC
184 chip superio/ite/it8716f
187 # Watchdog from CLKIN, CLKIN = 24 MHz
189 # Serial Flash (SPI only)
195 device pnp 2e.1 on # Com1
199 device pnp 2e.2 off # Com2
203 device pnp 2e.3 off # Parallel Port
207 device pnp 2e.4 on # EC
212 device pnp 2e.5 on # Keyboard
217 device pnp 2e.6 on # Mouse
220 device pnp 2e.7 on # GPIO, SPI flash
223 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
229 # pin 6,3,128,127,126 is GP63,64,65,66,67
231 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
235 # Serial Flash I/O (SPI only)
237 # watch dog force timeout (parallel flash only)
241 # GPIO pin set 1 disable internal pullup
243 # GPIO pin set 5 enable internal pullup
245 # SIO pin set 1 alternate function
247 # SIO pin set 2 mixed function
249 # SIO pin set 3 mixed function
251 # SIO pin set 4 alternate function
253 # SIO pin set 1 input mode
255 # SIO pin set 2 input mode
257 # SIO pin set 4 input mode
259 # Generate SMI# on EC IRQ
263 # HWMON alert beep pin location
266 device pnp 2e.8 off # MIDI
270 device pnp 2e.9 off # GAME
273 device pnp 2e.a off end # CIR
276 device pci 1.1 on # SM 0
277 chip drivers/generic/generic #dimm 0-0-0
280 chip drivers/generic/generic #dimm 0-0-1
283 chip drivers/generic/generic #dimm 0-1-0
286 chip drivers/generic/generic #dimm 0-1-1
289 chip drivers/generic/generic #dimm 1-0-0
292 chip drivers/generic/generic #dimm 1-0-1
295 chip drivers/generic/generic #dimm 1-1-0
298 chip drivers/generic/generic #dimm 1-1-1
302 #WTF?!? We already have device pci 1.1 in the section above
303 device pci 1.1 on # SM 1
304 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
305 # chip drivers/generic/generic #PCIXA Slot1
306 # device i2c 50 on end
308 # chip drivers/generic/generic #PCIXB Slot1
309 # device i2c 51 on end
311 # chip drivers/generic/generic #PCIXB Slot2
312 # device i2c 52 on end
314 # chip drivers/generic/generic #PCI Slot1
315 # device i2c 53 on end
317 # chip drivers/generic/generic #Master MCP55 PCI-E
318 # device i2c 54 on end
320 # chip drivers/generic/generic #Slave MCP55 PCI-E
321 # device i2c 55 on end
323 chip drivers/generic/generic #MAC EEPROM
328 device pci 2.0 on end # USB 1.1
329 device pci 2.1 on end # USB 2
330 device pci 4.0 on end # IDE
331 device pci 5.0 on end # SATA 0
332 device pci 5.1 on end # SATA 1
333 device pci 5.2 on end # SATA 2
334 device pci 6.0 on end # PCI
335 device pci 6.1 on end # AZA
336 device pci 8.0 on end # NIC
337 device pci 9.0 off end # NIC
338 device pci a.0 on end # PCI E 5
339 device pci b.0 on end # PCI E 4
340 device pci c.0 on end # PCI E 3
341 device pci d.0 on end # PCI E 2
342 device pci e.0 on end # PCI E 1
343 device pci f.0 on end # PCI E 0
344 register "ide0_enable" = "1"
345 register "sata0_enable" = "1"
346 register "sata1_enable" = "1"
347 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
348 register "mac_eeprom_addr" = "0x51"
350 end # device pci 18.0
351 device pci 18.0 on end # Link 1
352 device pci 18.0 on end
353 device pci 18.1 on end
354 device pci 18.2 on end
355 device pci 18.3 on end
360 # chip drivers/generic/debug
361 # device pnp 0.0 off end # chip name
362 # device pnp 0.1 on end # pci_regs_all
363 # device pnp 0.2 on end # mem
364 # device pnp 0.3 off end # cpuid
365 # device pnp 0.4 on end # smbus_regs_all
366 # device pnp 0.5 off end # dual core msr
367 # device pnp 0.6 off end # cache size
368 # device pnp 0.7 off end # tsc
369 # device pnp 0.8 off end # io
370 # device pnp 0.9 off end # io