src/mainboard/gigabyte/m57sli/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 include /config/failovercalculation.lb
  23
  24 arch i386 end
  25
  26 ##
  27 ## Build the objects we have code for in this directory.
  28 ##
  29
  30 driver mainboard.o
  31 #needed by irq_tables and mptable and acpi_tables
  32 object get_bus_conf.o
  33
  34 if HAVE_MP_TABLE object mptable.o end
  35 if HAVE_PIRQ_TABLE object irq_tables.o end
  36 #object reset.o
  37
  38         if CONFIG_USE_INIT
  39                 makerule ./cache_as_ram_auto.o
  40                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  41                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  42                 end
  43         else
  44                 makerule ./cache_as_ram_auto.inc
  45                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  46                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  47                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  48                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  49                 end
  50         end
  51
  52 if USE_FAILOVER_IMAGE
  53 else
  54     if CONFIG_AP_CODE_IN_CAR
  55         makerule ./apc_auto.o
  56                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
  57                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
  58         end
  59         ldscript /arch/i386/init/ldscript_apc.lb
  60     end
  61 end
  62
  63
  64 ##
  65 ## Build our 16 bit and 32 bit coreboot entry code
  66 ##
  67 if HAVE_FAILOVER_BOOT
  68     if USE_FAILOVER_IMAGE
  69         mainboardinit cpu/x86/16bit/entry16.inc
  70         ldscript /cpu/x86/16bit/entry16.lds
  71     end
  72 else
  73     if USE_FALLBACK_IMAGE
  74         mainboardinit cpu/x86/16bit/entry16.inc
  75         ldscript /cpu/x86/16bit/entry16.lds
  76     end
  77 end
  78
  79 mainboardinit cpu/x86/32bit/entry32.inc
  80
  81         if CONFIG_USE_INIT
  82                 ldscript /cpu/x86/32bit/entry32.lds
  83         end
  84
  85         if CONFIG_USE_INIT
  86                 ldscript /cpu/amd/car/cache_as_ram.lds
  87         end
  88
  89 ##
  90 ## Build our reset vector (This is where coreboot is entered)
  91 ##
  92 if HAVE_FAILOVER_BOOT
  93     if USE_FAILOVER_IMAGE
  94         mainboardinit cpu/x86/16bit/reset16.inc
  95         ldscript /cpu/x86/16bit/reset16.lds
  96     else
  97         mainboardinit cpu/x86/32bit/reset32.inc
  98         ldscript /cpu/x86/32bit/reset32.lds
  99     end
 100 else
 101     if USE_FALLBACK_IMAGE
 102         mainboardinit cpu/x86/16bit/reset16.inc
 103         ldscript /cpu/x86/16bit/reset16.lds
 104     else
 105         mainboardinit cpu/x86/32bit/reset32.inc
 106         ldscript /cpu/x86/32bit/reset32.lds
 107     end
 108 end
 109
 110 ##
 111 ## Include an id string (For safe flashing)
 112 ##
 113 mainboardinit southbridge/nvidia/mcp55/id.inc
 114 ldscript /southbridge/nvidia/mcp55/id.lds
 115
 116 ##
 117 ## ROMSTRAP table for MCP55
 118 ##
 119 if HAVE_FAILOVER_BOOT
 120     if USE_FAILOVER_IMAGE
 121         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 122         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 123     end
 124 else
 125     if USE_FALLBACK_IMAGE
 126         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 127         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 128     end
 129 end
 130
 131         ##
 132         ## Setup Cache-As-Ram
 133         ##
 134         mainboardinit cpu/amd/car/cache_as_ram.inc
 135
 136 ###
 137 ### This is the early phase of coreboot startup
 138 ### Things are delicate and we test to see if we should
 139 ### failover to another image.
 140 ###
 141 if HAVE_FAILOVER_BOOT
 142     if USE_FAILOVER_IMAGE
 143                 ldscript /arch/i386/lib/failover_failover.lds
 144     end
 145 else
 146     if USE_FALLBACK_IMAGE
 147                 ldscript /arch/i386/lib/failover.lds
 148     end
 149 end
 150
 151 if HAVE_FANCTL
 152         object fanctl.o
 153 end
 154
 155 ##
 156 ## Setup RAM
 157 ##
 158         if CONFIG_USE_INIT
 159                 initobject cache_as_ram_auto.o
 160         else
 161                 mainboardinit ./cache_as_ram_auto.inc
 162         end
 163
 164 ##
 165 ## Include the secondary Configuration files
 166 ##
 167 config chip.h
 168
 169 chip northbridge/amd/amdk8/root_complex
 170         device apic_cluster 0 on
 171                 chip cpu/amd/socket_AM2
 172                         device apic 0 on end
 173                 end
 174         end
 175         device pci_domain 0 on
 176                 chip northbridge/amd/amdk8 #mc0
 177                         device pci 18.0 on
 178                                 #  devices on link 0, link 0 == LDT 0
 179                                 chip southbridge/nvidia/mcp55
 180                                         device pci 0.0 on end   # HT
 181                                         device pci 1.0 on # LPC
 182                                                 chip superio/ite/it8716f
 183                                                         # Floppy and any LDN
 184                                                         device pnp 2e.0 off
 185                                                         # Watchdog from CLKIN, CLKIN = 24 MHz
 186                                                                 irq 0x23 = 0x11
 187                                                         # Serial Flash (SPI only)
 188                                                                 #0x24 = 0x1a
 189                                                                 io 0x60 = 0x3f0
 190                                                                 irq 0x70 = 6
 191                                                                 drq 0x74 = 2
 192                                                         end
 193                                                         device pnp 2e.1 on #  Com1
 194                                                                 io 0x60 = 0x3f8
 195                                                                 irq 0x70 = 4
 196                                                         end
 197                                                         device pnp 2e.2 off #  Com2
 198                                                                 io 0x60 = 0x2f8
 199                                                                 irq 0x70 = 3
 200                                                         end
 201                                                         device pnp 2e.3 off #  Parallel Port
 202                                                                 io 0x60 = 0x378
 203                                                                 irq 0x70 = 7
 204                                                         end
 205                                                         device pnp 2e.4 on #  EC
 206                                                                 io 0x60 = 0x290
 207                                                                 io 0x62 = 0x230
 208                                                                 irq 0x70 = 9
 209                                                         end
 210                                                         device pnp 2e.5 on #  Keyboard
 211                                                                 io 0x60 = 0x60
 212                                                                 io 0x62 = 0x64
 213                                                                 irq 0x70 = 1
 214                                                         end
 215                                                         device pnp 2e.6 on #  Mouse
 216                                                                 irq 0x70 = 12
 217                                                         end
 218                                                         device pnp 2e.7 on #  GPIO, SPI flash
 219                                                                 # pin 84 is not GP10
 220                                                                 irq 0x25 = 0x0
 221                                 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
 222                                                                 irq 0x26 = 0x43
 223                                                                 # pin 13 is GP35
 224                                                                 irq 0x27 = 0x20
 225                                                                 # pin 70 is not GP46
 226                                                                 #irq 0x28 = 0x0
 227                                 # pin 6,3,128,127,126 is GP63,64,65,66,67
 228                                                                 irq 0x29 = 0x81
 229                                 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
 230                                                                 #irq 0x2c = 0x1f
 231                                 # Simple I/O base
 232                                                                 io 0x62 = 0x800
 233                                 # Serial Flash I/O (SPI only)
 234                                                                 io 0x64 = 0x820
 235                                 # watch dog force timeout (parallel flash only)
 236                                                                 #irq 0x71 = 0x1
 237                                                                 # No WDT interrupt
 238                                                                 irq 0x72 = 0x0
 239                                         # GPIO pin set 1 disable internal pullup
 240                                                                 irq 0xb8 = 0x0
 241                                         # GPIO pin set 5 enable internal pullup
 242                                                                 irq 0xbc = 0x01
 243                                         # SIO pin set 1 alternate function
 244                                                                 #irq 0xc0 = 0x0
 245                                         # SIO pin set 2 mixed function
 246                                                                 irq 0xc1 = 0x43
 247                                         # SIO pin set 3 mixed function
 248                                                                 irq 0xc2 = 0x20
 249                                         # SIO pin set 4 alternate function
 250                                                                 #irq 0xc3 = 0x0
 251                                         # SIO pin set 1 input mode
 252                                                                 #irq 0xc8 = 0x0
 253                                         # SIO pin set 2 input mode
 254                                                                 irq 0xc9 = 0x0
 255                                         # SIO pin set 4 input mode
 256                                                                 #irq 0xcb = 0x0
 257                                         # Generate SMI# on EC IRQ
 258                                                                 #irq 0xf0 = 0x10
 259                                         # SMI# level trigger
 260                                                                 #irq 0xf1 = 0x40
 261                                         # HWMON alert beep pin location
 262                                                                 irq 0xf6 = 0x28
 263                                                         end
 264                                                         device pnp 2e.8 off #  MIDI
 265                                                                 io 0x60 = 0x300
 266                                                                 irq 0x70 = 10
 267                                                         end
 268                                                         device pnp 2e.9 off #  GAME
 269                                                                 io 0x60 = 0x220
 270                                                         end
 271                                                         device pnp 2e.a off end #  CIR
 272                                                 end
 273                                         end
 274                                         device pci 1.1 on # SM 0
 275                                                 chip drivers/generic/generic #dimm 0-0-0
 276                                                         device i2c 50 on end
 277                                                 end
 278                                                 chip drivers/generic/generic #dimm 0-0-1
 279                                                         device i2c 51 on end
 280                                                 end
 281                                                 chip drivers/generic/generic #dimm 0-1-0
 282                                                         device i2c 52 on end
 283                                                 end
 284                                                 chip drivers/generic/generic #dimm 0-1-1
 285                                                         device i2c 53 on end
 286                                                 end
 287                                                 chip drivers/generic/generic #dimm 1-0-0
 288                                                         device i2c 54 on end
 289                                                 end
 290                                                 chip drivers/generic/generic #dimm 1-0-1
 291                                                         device i2c 55 on end
 292                                                 end
 293                                                 chip drivers/generic/generic #dimm 1-1-0
 294                                                         device i2c 56 on end
 295                                                 end
 296                                                 chip drivers/generic/generic #dimm 1-1-1
 297                                                         device i2c 57 on end
 298                                                 end
 299                                         end # SM
 300 #WTF?!? We already have device pci 1.1 in the section above
 301                                         device pci 1.1 on # SM 1
 302 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 303 #                                                chip drivers/generic/generic #PCIXA Slot1
 304 #                                                        device i2c 50 on end
 305 #                                                end
 306 #                                                chip drivers/generic/generic #PCIXB Slot1
 307 #                                                        device i2c 51 on end
 308 #                                                end
 309 #                                                chip drivers/generic/generic #PCIXB Slot2
 310 #                                                        device i2c 52 on end
 311 #                                                end
 312 #                                                chip drivers/generic/generic #PCI Slot1
 313 #                                                        device i2c 53 on end
 314 #                                                end
 315 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 316 #                                                        device i2c 54 on end
 317 #                                                end
 318 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 319 #                                                        device i2c 55 on end
 320 #                                                end
 321                                                 chip drivers/generic/generic #MAC EEPROM
 322                                                         device i2c 51 on end
 323                                                 end
 324
 325                                         end # SM
 326                                         device pci 2.0 on end # USB 1.1
 327                                         device pci 2.1 on end # USB 2
 328                                         device pci 4.0 on end # IDE
 329                                         device pci 5.0 on end # SATA 0
 330                                         device pci 5.1 on end # SATA 1
 331                                         device pci 5.2 on end # SATA 2
 332                                         device pci 6.0 on end # PCI
 333                                         device pci 6.1 on end # AZA
 334                                         device pci 8.0 on end # NIC
 335                                         device pci 9.0 off end # NIC
 336                                         device pci a.0 on end # PCI E 5
 337                                         device pci b.0 on end # PCI E 4
 338                                         device pci c.0 on end # PCI E 3
 339                                         device pci d.0 on end # PCI E 2
 340                                         device pci e.0 on end # PCI E 1
 341                                         device pci f.0 on end # PCI E 0
 342                                         register "ide0_enable" = "1"
 343                                         register "sata0_enable" = "1"
 344                                         register "sata1_enable" = "1"
 345                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 346                                         register "mac_eeprom_addr" = "0x51"
 347                                 end
 348                         end #  device pci 18.0
 349                         device pci 18.0 on end # Link 1
 350                         device pci 18.0 on end
 351                         device pci 18.1 on end
 352                         device pci 18.2 on end
 353                         device pci 18.3 on end
 354                 end # mc0
 355
 356         end # PCI domain
 357
 358 #       chip drivers/generic/debug
 359 #               device pnp 0.0 off end # chip name
 360 #                device pnp 0.1 on end # pci_regs_all
 361 #                device pnp 0.2 on end # mem
 362 #                device pnp 0.3 off end # cpuid
 363 #                device pnp 0.4 on end # smbus_regs_all
 364 #                device pnp 0.5 off end # dual core msr
 365 #                device pnp 0.6 off end # cache size
 366 #               device pnp 0.7 off end # tsc
 367 #                device pnp 0.8 off  end # io
 368 #                device pnp 0.9 off end # io
 369 #       end
 370 end #root_complex