src/mainboard/gigabyte/m57sli/Config.lb

   1 ##
   2 ## This file is part of the LinuxBIOS project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ##
  23 ## Compute the location and size of where this firmware image
  24 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
  25 ##
  26 if USE_FAILOVER_IMAGE
  27         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  28         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  29 else
  30     if USE_FALLBACK_IMAGE
  31         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  32         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33     else
  34         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35         default ROM_SECTION_OFFSET = 0
  36     end
  37 end
  38
  39 ##
  40 ## Compute the start location and size size of
  41 ## The linuxBIOS bootloader.
  42 ##
  43 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  45
  46 ##
  47 ## Compute where this copy of linuxBIOS will start in the boot rom
  48 ##
  49 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  50
  51 ##
  52 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  53 ## execution speed.
  54 ##
  55 ## XIP_ROM_SIZE must be a power of 2.
  56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  57 ##
  58 default XIP_ROM_SIZE=65536
  59
  60 if USE_FAILOVER_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  62 else
  63     if USE_FALLBACK_IMAGE
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  65     else
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  67     end
  68 end
  69
  70 arch i386 end
  71
  72 ##
  73 ## Build the objects we have code for in this directory.
  74 ##
  75
  76 driver mainboard.o
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE object mptable.o end
  81 if HAVE_PIRQ_TABLE object irq_tables.o end
  82 #object reset.o
  83 if USE_DCACHE_RAM
  84
  85         if CONFIG_USE_INIT
  86                 makerule ./cache_as_ram_auto.o
  87                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  88                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  89                 end
  90         else
  91                 makerule ./cache_as_ram_auto.inc
  92                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  93                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  94                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  95                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  96                 end
  97         end
  98
  99 end
 100
 101 if USE_FAILOVER_IMAGE
 102 else
 103     if CONFIG_AP_CODE_IN_CAR
 104         makerule ./apc_auto.o
 105                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 106                 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 107         end
 108         ldscript /arch/i386/init/ldscript_apc.lb
 109     end
 110 end
 111
 112
 113 ##
 114 ## Build our 16 bit and 32 bit linuxBIOS entry code
 115 ##
 116 if HAVE_FAILOVER_BOOT
 117     if USE_FAILOVER_IMAGE
 118         mainboardinit cpu/x86/16bit/entry16.inc
 119         ldscript /cpu/x86/16bit/entry16.lds
 120     end
 121 else
 122     if USE_FALLBACK_IMAGE
 123         mainboardinit cpu/x86/16bit/entry16.inc
 124         ldscript /cpu/x86/16bit/entry16.lds
 125     end
 126 end
 127
 128 mainboardinit cpu/x86/32bit/entry32.inc
 129
 130 if USE_DCACHE_RAM
 131         if CONFIG_USE_INIT
 132                 ldscript /cpu/x86/32bit/entry32.lds
 133         end
 134
 135         if CONFIG_USE_INIT
 136                 ldscript /cpu/amd/car/cache_as_ram.lds
 137         end
 138 end
 139
 140
 141 ##
 142 ## Build our reset vector (This is where linuxBIOS is entered)
 143 ##
 144 if HAVE_FAILOVER_BOOT
 145     if USE_FAILOVER_IMAGE
 146         mainboardinit cpu/x86/16bit/reset16.inc
 147         ldscript /cpu/x86/16bit/reset16.lds
 148     else
 149         mainboardinit cpu/x86/32bit/reset32.inc
 150         ldscript /cpu/x86/32bit/reset32.lds
 151     end
 152 else
 153     if USE_FALLBACK_IMAGE
 154         mainboardinit cpu/x86/16bit/reset16.inc
 155         ldscript /cpu/x86/16bit/reset16.lds
 156     else
 157         mainboardinit cpu/x86/32bit/reset32.inc
 158         ldscript /cpu/x86/32bit/reset32.lds
 159     end
 160 end
 161
 162 ##
 163 ## Include an id string (For safe flashing)
 164 ##
 165 mainboardinit southbridge/nvidia/mcp55/id.inc
 166 ldscript /southbridge/nvidia/mcp55/id.lds
 167
 168 ##
 169 ## ROMSTRAP table for MCP55
 170 ##
 171 if HAVE_FAILOVER_BOOT
 172     if USE_FAILOVER_IMAGE
 173         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 174         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 175     end
 176 else
 177     if USE_FALLBACK_IMAGE
 178         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 179         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 180     end
 181 end
 182
 183 if USE_DCACHE_RAM
 184         ##
 185         ## Setup Cache-As-Ram
 186         ##
 187         mainboardinit cpu/amd/car/cache_as_ram.inc
 188 end
 189
 190 ###
 191 ### This is the early phase of linuxBIOS startup
 192 ### Things are delicate and we test to see if we should
 193 ### failover to another image.
 194 ###
 195 if HAVE_FAILOVER_BOOT
 196     if USE_FAILOVER_IMAGE
 197         if USE_DCACHE_RAM
 198                 ldscript /arch/i386/lib/failover_failover.lds
 199         end
 200     end
 201 else
 202     if USE_FALLBACK_IMAGE
 203         if USE_DCACHE_RAM
 204                 ldscript /arch/i386/lib/failover.lds
 205         end
 206     end
 207 end
 208
 209 ##
 210 ## Setup RAM
 211 ##
 212 if USE_DCACHE_RAM
 213
 214         if CONFIG_USE_INIT
 215                 initobject cache_as_ram_auto.o
 216         else
 217                 mainboardinit ./cache_as_ram_auto.inc
 218         end
 219 end
 220
 221 ##
 222 ## Include the secondary Configuration files
 223 ##
 224 if CONFIG_CHIP_NAME
 225         config chip.h
 226 end
 227
 228 chip northbridge/amd/amdk8/root_complex
 229         device apic_cluster 0 on
 230                 chip cpu/amd/socket_AM2
 231                         device apic 0 on end
 232                 end
 233         end
 234         device pci_domain 0 on
 235                 chip northbridge/amd/amdk8 #mc0
 236                         device pci 18.0 on
 237                                 #  devices on link 0, link 0 == LDT 0
 238                                 chip southbridge/nvidia/mcp55
 239                                         device pci 0.0 on end   # HT
 240                                         device pci 1.0 on # LPC
 241                                                 chip superio/ite/it8716f
 242                                                         # Floppy and any LDN
 243                                                         device pnp 2e.0 off
 244                                                         # Watchdog from CLKIN, CLKIN = 24 MHz
 245                                                                 irq 0x23 = 0x11
 246                                                         # Serial Flash (SPI only)
 247                                                                 #0x24 = 0x1a
 248                                                                 io 0x60 = 0x3f0
 249                                                                 irq 0x70 = 6
 250                                                                 drq 0x74 = 2
 251                                                         end
 252                                                         device pnp 2e.1 on #  Com1
 253                                                                 io 0x60 = 0x3f8
 254                                                                 irq 0x70 = 4
 255                                                         end
 256                                                         device pnp 2e.2 off #  Com2
 257                                                                 io 0x60 = 0x2f8
 258                                                                 irq 0x70 = 3
 259                                                         end
 260                                                         device pnp 2e.3 off #  Parallel Port
 261                                                                 io 0x60 = 0x378
 262                                                                 irq 0x70 = 7
 263                                                         end
 264                                                         device pnp 2e.4 on #  EC
 265                                                                 io 0x60 = 0x290
 266                                                                 io 0x62 = 0x230
 267                                                                 irq 0x70 = 9
 268                                                         end
 269                                                         device pnp 2e.5 on #  Keyboard
 270                                                                 io 0x60 = 0x60
 271                                                                 io 0x62 = 0x64
 272                                                                 irq 0x70 = 1
 273                                                         end
 274                                                         device pnp 2e.6 on #  Mouse
 275                                                                 irq 0x70 = 12
 276                                                         end
 277                                                         device pnp 2e.7 on #  GPIO, SPI flash
 278                                                                 # pin 84 is not GP10
 279                                                                 irq 0x25 = 0x0
 280                                 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
 281                                                                 irq 0x26 = 0x43
 282                                                                 # pin 13 is GP35
 283                                                                 irq 0x27 = 0x20
 284                                                                 # pin 70 is not GP46
 285                                                                 #irq 0x28 = 0x0
 286                                 # pin 6,3,128,127,126 is GP63,64,65,66,67
 287                                                                 irq 0x29 = 0x81
 288                                 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
 289                                                                 #irq 0x2c = 0x1f
 290                                 # Simple I/O base
 291                                                                 io 0x62 = 0x800
 292                                 # Serial Flash I/O (SPI only)
 293                                                                 #io 0x64 = 0x820
 294                                 # watch dog force timeout (parallel flash only)
 295                                                                 #irq 0x71 = 0x1
 296                                                                 # No WDT interrupt
 297                                                                 irq 0x72 = 0x0
 298                                         # GPIO pin set 1 disable internal pullup
 299                                                                 irq 0xb8 = 0x0
 300                                         # GPIO pin set 5 enable internal pullup
 301                                                                 irq 0xbc = 0x01
 302                                         # SIO pin set 1 alternate function
 303                                                                 #irq 0xc0 = 0x0
 304                                         # SIO pin set 2 mixed function
 305                                                                 irq 0xc1 = 0x43
 306                                         # SIO pin set 3 mixed function
 307                                                                 irq 0xc2 = 0x20
 308                                         # SIO pin set 4 alternate function
 309                                                                 #irq 0xc3 = 0x0
 310                                         # SIO pin set 1 input mode
 311                                                                 #irq 0xc8 = 0x0
 312                                         # SIO pin set 2 mixed input/output mode
 313                                                                 irq 0xc9 = 0x0
 314                                         # SIO pin set 4 input mode
 315                                                                 #irq 0xcb = 0x0
 316                                         # Generate SMI# on EC IRQ
 317                                                                 #irq 0xf0 = 0x10
 318                                         # SMI# level trigger
 319                                                                 #irq 0xf1 = 0x40
 320                                         # HWMON alert beep pin location
 321                                                                 irq 0xf6 = 0x28
 322                                                         end
 323                                                         device pnp 2e.8 off #  MIDI
 324                                                                 io 0x60 = 0x300
 325                                                                 irq 0x70 = 10
 326                                                         end
 327                                                         device pnp 2e.9 off #  GAME
 328                                                                 io 0x60 = 0x220
 329                                                         end
 330                                                         device pnp 2e.a off end #  CIR
 331                                                 end
 332                                         end
 333                                         device pci 1.1 on # SM 0
 334                                                 chip drivers/generic/generic #dimm 0-0-0
 335                                                         device i2c 50 on end
 336                                                 end
 337                                                 chip drivers/generic/generic #dimm 0-0-1
 338                                                         device i2c 51 on end
 339                                                 end
 340                                                 chip drivers/generic/generic #dimm 0-1-0
 341                                                         device i2c 52 on end
 342                                                 end
 343                                                 chip drivers/generic/generic #dimm 0-1-1
 344                                                         device i2c 53 on end
 345                                                 end
 346                                                 chip drivers/generic/generic #dimm 1-0-0
 347                                                         device i2c 54 on end
 348                                                 end
 349                                                 chip drivers/generic/generic #dimm 1-0-1
 350                                                         device i2c 55 on end
 351                                                 end
 352                                                 chip drivers/generic/generic #dimm 1-1-0
 353                                                         device i2c 56 on end
 354                                                 end
 355                                                 chip drivers/generic/generic #dimm 1-1-1
 356                                                         device i2c 57 on end
 357                                                 end
 358                                         end # SM
 359 #WTF?!? We already have device pci 1.1 in the section above
 360                                         device pci 1.1 on # SM 1
 361 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 362 #                                                chip drivers/generic/generic #PCIXA Slot1
 363 #                                                        device i2c 50 on end
 364 #                                                end
 365 #                                                chip drivers/generic/generic #PCIXB Slot1
 366 #                                                        device i2c 51 on end
 367 #                                                end
 368 #                                                chip drivers/generic/generic #PCIXB Slot2
 369 #                                                        device i2c 52 on end
 370 #                                                end
 371 #                                                chip drivers/generic/generic #PCI Slot1
 372 #                                                        device i2c 53 on end
 373 #                                                end
 374 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 375 #                                                        device i2c 54 on end
 376 #                                                end
 377 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 378 #                                                        device i2c 55 on end
 379 #                                                end
 380                                                 chip drivers/generic/generic #MAC EEPROM
 381                                                         device i2c 51 on end
 382                                                 end
 383
 384                                         end # SM
 385                                         device pci 2.0 on end # USB 1.1
 386                                         device pci 2.1 on end # USB 2
 387                                         device pci 4.0 on end # IDE
 388                                         device pci 5.0 on end # SATA 0
 389                                         device pci 5.1 on end # SATA 1
 390                                         device pci 5.2 on end # SATA 2
 391                                         device pci 6.0 on end # PCI
 392                                         device pci 6.1 on end # AZA
 393                                         device pci 8.0 on end # NIC
 394                                         device pci 9.0 off end # NIC
 395                                         device pci a.0 on end # PCI E 5
 396                                         device pci b.0 on end # PCI E 4
 397                                         device pci c.0 on end # PCI E 3
 398                                         device pci d.0 on end # PCI E 2
 399                                         device pci e.0 on end # PCI E 1
 400                                         device pci f.0 on end # PCI E 0
 401                                         register "ide0_enable" = "1"
 402                                         register "sata0_enable" = "1"
 403                                         register "sata1_enable" = "1"
 404                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 405                                         register "mac_eeprom_addr" = "0x51"
 406                                 end
 407                         end #  device pci 18.0
 408                         device pci 18.0 on end # Link 1
 409                         device pci 18.0 on end
 410                         device pci 18.1 on end
 411                         device pci 18.2 on end
 412                         device pci 18.3 on end
 413                 end # mc0
 414
 415         end # PCI domain
 416
 417 #       chip drivers/generic/debug
 418 #               device pnp 0.0 off end # chip name
 419 #                device pnp 0.1 on end # pci_regs_all
 420 #                device pnp 0.2 on end # mem
 421 #                device pnp 0.3 off end # cpuid
 422 #                device pnp 0.4 on end # smbus_regs_all
 423 #                device pnp 0.5 off end # dual core msr
 424 #                device pnp 0.6 off end # cache size
 425 #               device pnp 0.7 off end # tsc
 426 #                device pnp 0.8 off  end # io
 427 #                device pnp 0.9 off end # io
 428 #       end
 429 end #root_complex