src/mainboard/gigabyte/m57sli/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ##
  23 ## Compute the location and size of where this firmware image
  24 ## (coreboot plus bootloader) will live in the boot rom chip.
  25 ##
  26 if USE_FAILOVER_IMAGE
  27         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  28         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  29 else
  30     if USE_FALLBACK_IMAGE
  31         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  32         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33     else
  34         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35         default ROM_SECTION_OFFSET = 0
  36     end
  37 end
  38
  39 ##
  40 ## Compute the start location and size size of
  41 ## The coreboot bootloader.
  42 ##
  43 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  45
  46 ##
  47 ## Compute where this copy of coreboot will start in the boot rom
  48 ##
  49 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  50
  51 ##
  52 ## Compute a range of ROM that can cached to speed up coreboot,
  53 ## execution speed.
  54 ##
  55 ## XIP_ROM_SIZE must be a power of 2.
  56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  57 ##
  58 default XIP_ROM_SIZE=65536
  59
  60 if USE_FAILOVER_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  62 else
  63     if USE_FALLBACK_IMAGE
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  65     else
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  67     end
  68 end
  69
  70 arch i386 end
  71
  72 ##
  73 ## Build the objects we have code for in this directory.
  74 ##
  75
  76 driver mainboard.o
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE object mptable.o end
  81 if HAVE_PIRQ_TABLE object irq_tables.o end
  82 #object reset.o
  83
  84         if CONFIG_USE_INIT
  85                 makerule ./cache_as_ram_auto.o
  86                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  87                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  88                 end
  89         else
  90                 makerule ./cache_as_ram_auto.inc
  91                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  92                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  93                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  94                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  95                 end
  96         end
  97
  98 if USE_FAILOVER_IMAGE
  99 else
 100     if CONFIG_AP_CODE_IN_CAR
 101         makerule ./apc_auto.o
 102                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 103                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
 104         end
 105         ldscript /arch/i386/init/ldscript_apc.lb
 106     end
 107 end
 108
 109
 110 ##
 111 ## Build our 16 bit and 32 bit coreboot entry code
 112 ##
 113 if HAVE_FAILOVER_BOOT
 114     if USE_FAILOVER_IMAGE
 115         mainboardinit cpu/x86/16bit/entry16.inc
 116         ldscript /cpu/x86/16bit/entry16.lds
 117     end
 118 else
 119     if USE_FALLBACK_IMAGE
 120         mainboardinit cpu/x86/16bit/entry16.inc
 121         ldscript /cpu/x86/16bit/entry16.lds
 122     end
 123 end
 124
 125 mainboardinit cpu/x86/32bit/entry32.inc
 126
 127         if CONFIG_USE_INIT
 128                 ldscript /cpu/x86/32bit/entry32.lds
 129         end
 130
 131         if CONFIG_USE_INIT
 132                 ldscript /cpu/amd/car/cache_as_ram.lds
 133         end
 134
 135 ##
 136 ## Build our reset vector (This is where coreboot is entered)
 137 ##
 138 if HAVE_FAILOVER_BOOT
 139     if USE_FAILOVER_IMAGE
 140         mainboardinit cpu/x86/16bit/reset16.inc
 141         ldscript /cpu/x86/16bit/reset16.lds
 142     else
 143         mainboardinit cpu/x86/32bit/reset32.inc
 144         ldscript /cpu/x86/32bit/reset32.lds
 145     end
 146 else
 147     if USE_FALLBACK_IMAGE
 148         mainboardinit cpu/x86/16bit/reset16.inc
 149         ldscript /cpu/x86/16bit/reset16.lds
 150     else
 151         mainboardinit cpu/x86/32bit/reset32.inc
 152         ldscript /cpu/x86/32bit/reset32.lds
 153     end
 154 end
 155
 156 ##
 157 ## Include an id string (For safe flashing)
 158 ##
 159 mainboardinit southbridge/nvidia/mcp55/id.inc
 160 ldscript /southbridge/nvidia/mcp55/id.lds
 161
 162 ##
 163 ## ROMSTRAP table for MCP55
 164 ##
 165 if HAVE_FAILOVER_BOOT
 166     if USE_FAILOVER_IMAGE
 167         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 168         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 169     end
 170 else
 171     if USE_FALLBACK_IMAGE
 172         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 173         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 174     end
 175 end
 176
 177         ##
 178         ## Setup Cache-As-Ram
 179         ##
 180         mainboardinit cpu/amd/car/cache_as_ram.inc
 181
 182 ###
 183 ### This is the early phase of coreboot startup
 184 ### Things are delicate and we test to see if we should
 185 ### failover to another image.
 186 ###
 187 if HAVE_FAILOVER_BOOT
 188     if USE_FAILOVER_IMAGE
 189                 ldscript /arch/i386/lib/failover_failover.lds
 190     end
 191 else
 192     if USE_FALLBACK_IMAGE
 193                 ldscript /arch/i386/lib/failover.lds
 194     end
 195 end
 196
 197 if HAVE_FANCTL
 198         object fanctl.o
 199 end
 200
 201 ##
 202 ## Setup RAM
 203 ##
 204         if CONFIG_USE_INIT
 205                 initobject cache_as_ram_auto.o
 206         else
 207                 mainboardinit ./cache_as_ram_auto.inc
 208         end
 209
 210 ##
 211 ## Include the secondary Configuration files
 212 ##
 213 config chip.h
 214
 215 chip northbridge/amd/amdk8/root_complex
 216         device apic_cluster 0 on
 217                 chip cpu/amd/socket_AM2
 218                         device apic 0 on end
 219                 end
 220         end
 221         device pci_domain 0 on
 222                 chip northbridge/amd/amdk8 #mc0
 223                         device pci 18.0 on
 224                                 #  devices on link 0, link 0 == LDT 0
 225                                 chip southbridge/nvidia/mcp55
 226                                         device pci 0.0 on end   # HT
 227                                         device pci 1.0 on # LPC
 228                                                 chip superio/ite/it8716f
 229                                                         # Floppy and any LDN
 230                                                         device pnp 2e.0 off
 231                                                         # Watchdog from CLKIN, CLKIN = 24 MHz
 232                                                                 irq 0x23 = 0x11
 233                                                         # Serial Flash (SPI only)
 234                                                                 #0x24 = 0x1a
 235                                                                 io 0x60 = 0x3f0
 236                                                                 irq 0x70 = 6
 237                                                                 drq 0x74 = 2
 238                                                         end
 239                                                         device pnp 2e.1 on #  Com1
 240                                                                 io 0x60 = 0x3f8
 241                                                                 irq 0x70 = 4
 242                                                         end
 243                                                         device pnp 2e.2 off #  Com2
 244                                                                 io 0x60 = 0x2f8
 245                                                                 irq 0x70 = 3
 246                                                         end
 247                                                         device pnp 2e.3 off #  Parallel Port
 248                                                                 io 0x60 = 0x378
 249                                                                 irq 0x70 = 7
 250                                                         end
 251                                                         device pnp 2e.4 on #  EC
 252                                                                 io 0x60 = 0x290
 253                                                                 io 0x62 = 0x230
 254                                                                 irq 0x70 = 9
 255                                                         end
 256                                                         device pnp 2e.5 on #  Keyboard
 257                                                                 io 0x60 = 0x60
 258                                                                 io 0x62 = 0x64
 259                                                                 irq 0x70 = 1
 260                                                         end
 261                                                         device pnp 2e.6 on #  Mouse
 262                                                                 irq 0x70 = 12
 263                                                         end
 264                                                         device pnp 2e.7 on #  GPIO, SPI flash
 265                                                                 # pin 84 is not GP10
 266                                                                 irq 0x25 = 0x0
 267                                 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
 268                                                                 irq 0x26 = 0x43
 269                                                                 # pin 13 is GP35
 270                                                                 irq 0x27 = 0x20
 271                                                                 # pin 70 is not GP46
 272                                                                 #irq 0x28 = 0x0
 273                                 # pin 6,3,128,127,126 is GP63,64,65,66,67
 274                                                                 irq 0x29 = 0x81
 275                                 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
 276                                                                 #irq 0x2c = 0x1f
 277                                 # Simple I/O base
 278                                                                 io 0x62 = 0x800
 279                                 # Serial Flash I/O (SPI only)
 280                                                                 io 0x64 = 0x820
 281                                 # watch dog force timeout (parallel flash only)
 282                                                                 #irq 0x71 = 0x1
 283                                                                 # No WDT interrupt
 284                                                                 irq 0x72 = 0x0
 285                                         # GPIO pin set 1 disable internal pullup
 286                                                                 irq 0xb8 = 0x0
 287                                         # GPIO pin set 5 enable internal pullup
 288                                                                 irq 0xbc = 0x01
 289                                         # SIO pin set 1 alternate function
 290                                                                 #irq 0xc0 = 0x0
 291                                         # SIO pin set 2 mixed function
 292                                                                 irq 0xc1 = 0x43
 293                                         # SIO pin set 3 mixed function
 294                                                                 irq 0xc2 = 0x20
 295                                         # SIO pin set 4 alternate function
 296                                                                 #irq 0xc3 = 0x0
 297                                         # SIO pin set 1 input mode
 298                                                                 #irq 0xc8 = 0x0
 299                                         # SIO pin set 2 input mode
 300                                                                 irq 0xc9 = 0x0
 301                                         # SIO pin set 4 input mode
 302                                                                 #irq 0xcb = 0x0
 303                                         # Generate SMI# on EC IRQ
 304                                                                 #irq 0xf0 = 0x10
 305                                         # SMI# level trigger
 306                                                                 #irq 0xf1 = 0x40
 307                                         # HWMON alert beep pin location
 308                                                                 irq 0xf6 = 0x28
 309                                                         end
 310                                                         device pnp 2e.8 off #  MIDI
 311                                                                 io 0x60 = 0x300
 312                                                                 irq 0x70 = 10
 313                                                         end
 314                                                         device pnp 2e.9 off #  GAME
 315                                                                 io 0x60 = 0x220
 316                                                         end
 317                                                         device pnp 2e.a off end #  CIR
 318                                                 end
 319                                         end
 320                                         device pci 1.1 on # SM 0
 321                                                 chip drivers/generic/generic #dimm 0-0-0
 322                                                         device i2c 50 on end
 323                                                 end
 324                                                 chip drivers/generic/generic #dimm 0-0-1
 325                                                         device i2c 51 on end
 326                                                 end
 327                                                 chip drivers/generic/generic #dimm 0-1-0
 328                                                         device i2c 52 on end
 329                                                 end
 330                                                 chip drivers/generic/generic #dimm 0-1-1
 331                                                         device i2c 53 on end
 332                                                 end
 333                                                 chip drivers/generic/generic #dimm 1-0-0
 334                                                         device i2c 54 on end
 335                                                 end
 336                                                 chip drivers/generic/generic #dimm 1-0-1
 337                                                         device i2c 55 on end
 338                                                 end
 339                                                 chip drivers/generic/generic #dimm 1-1-0
 340                                                         device i2c 56 on end
 341                                                 end
 342                                                 chip drivers/generic/generic #dimm 1-1-1
 343                                                         device i2c 57 on end
 344                                                 end
 345                                         end # SM
 346 #WTF?!? We already have device pci 1.1 in the section above
 347                                         device pci 1.1 on # SM 1
 348 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 349 #                                                chip drivers/generic/generic #PCIXA Slot1
 350 #                                                        device i2c 50 on end
 351 #                                                end
 352 #                                                chip drivers/generic/generic #PCIXB Slot1
 353 #                                                        device i2c 51 on end
 354 #                                                end
 355 #                                                chip drivers/generic/generic #PCIXB Slot2
 356 #                                                        device i2c 52 on end
 357 #                                                end
 358 #                                                chip drivers/generic/generic #PCI Slot1
 359 #                                                        device i2c 53 on end
 360 #                                                end
 361 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 362 #                                                        device i2c 54 on end
 363 #                                                end
 364 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 365 #                                                        device i2c 55 on end
 366 #                                                end
 367                                                 chip drivers/generic/generic #MAC EEPROM
 368                                                         device i2c 51 on end
 369                                                 end
 370
 371                                         end # SM
 372                                         device pci 2.0 on end # USB 1.1
 373                                         device pci 2.1 on end # USB 2
 374                                         device pci 4.0 on end # IDE
 375                                         device pci 5.0 on end # SATA 0
 376                                         device pci 5.1 on end # SATA 1
 377                                         device pci 5.2 on end # SATA 2
 378                                         device pci 6.0 on end # PCI
 379                                         device pci 6.1 on end # AZA
 380                                         device pci 8.0 on end # NIC
 381                                         device pci 9.0 off end # NIC
 382                                         device pci a.0 on end # PCI E 5
 383                                         device pci b.0 on end # PCI E 4
 384                                         device pci c.0 on end # PCI E 3
 385                                         device pci d.0 on end # PCI E 2
 386                                         device pci e.0 on end # PCI E 1
 387                                         device pci f.0 on end # PCI E 0
 388                                         register "ide0_enable" = "1"
 389                                         register "sata0_enable" = "1"
 390                                         register "sata1_enable" = "1"
 391                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 392                                         register "mac_eeprom_addr" = "0x51"
 393                                 end
 394                         end #  device pci 18.0
 395                         device pci 18.0 on end # Link 1
 396                         device pci 18.0 on end
 397                         device pci 18.1 on end
 398                         device pci 18.2 on end
 399                         device pci 18.3 on end
 400                 end # mc0
 401
 402         end # PCI domain
 403
 404 #       chip drivers/generic/debug
 405 #               device pnp 0.0 off end # chip name
 406 #                device pnp 0.1 on end # pci_regs_all
 407 #                device pnp 0.2 on end # mem
 408 #                device pnp 0.3 off end # cpuid
 409 #                device pnp 0.4 on end # smbus_regs_all
 410 #                device pnp 0.5 off end # dual core msr
 411 #                device pnp 0.6 off end # cache size
 412 #               device pnp 0.7 off end # tsc
 413 #                device pnp 0.8 off  end # io
 414 #                device pnp 0.9 off end # io
 415 #       end
 416 end #root_complex