2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <device/pci.h>
29 #include <cpu/amd/amdk8_sysconf.h>
31 extern unsigned char bus_isa;
32 extern unsigned char bus_sis966[8]; //1
34 extern unsigned apicid_sis966;
36 extern unsigned bus_type[256];
38 static void *smp_write_config_table(void *v)
40 struct mp_config_table *mc;
44 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 mptable_init(mc, "GA-2761GXDK ", LAPIC_ADDR);
48 smp_write_processors(mc);
54 /* define bus and isa numbers */
55 for(j= 0; j < 256 ; j++) {
57 smp_write_bus(mc, j, "PCI ");
59 smp_write_bus(mc, bus_isa, "ISA ");
61 /*I/O APICs: APIC ID Version State Address*/
67 dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
69 res = find_resource(dev, PCI_BASE_ADDRESS_1);
71 smp_write_ioapic(mc, apicid_sis966, 0x11, res->base);
75 pci_write_config32(dev, 0x7c, dword);
78 pci_write_config32(dev, 0x80, dword);
81 pci_write_config32(dev, 0x84, dword);
86 mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
88 /* PCI interrupts are level triggered, and are
89 * associated with a specific bus/device/function tuple.
91 #define PCI_INT(bus, dev, fn, pin) \
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
94 PCI_INT(0, sbdn+1, 1, 0xa);
95 PCI_INT(0, sbdn+2, 0, 0x16); // 22
96 PCI_INT(0, sbdn+2, 1, 0x17); // 23
97 PCI_INT(0, sbdn+6, 1, 0x17); // 23
98 PCI_INT(0, sbdn+5, 0, 0x14); // 20
99 PCI_INT(0, sbdn+5, 1, 0x17); // 23
100 PCI_INT(0, sbdn+5, 2, 0x15); // 21
101 PCI_INT(0, sbdn+8, 0, 0x16); // 22
103 for(j=7; j>=2; j--) {
104 if(!bus_sis966[j]) continue;
106 PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
112 PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
115 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
116 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
117 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
118 /* There is no extension information... */
120 /* Compute the checksums */
121 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
122 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
123 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
124 mc, smp_next_mpe_entry(mc));
125 return smp_next_mpe_entry(mc);
128 unsigned long write_smp_table(unsigned long addr)
131 v = smp_write_floating_table(addr);
132 return (unsigned long)smp_write_config_table(v);