2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #define RAMINIT_SYSINFO 1
28 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
30 #define SET_NB_CFG_54 1
33 #define QRANK_DIMM_SUPPORT 1
35 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
38 #include <device/pci_def.h>
39 #include <device/pci_ids.h>
41 #include <device/pnp_def.h>
42 #include <arch/romcc_io.h>
43 #include <cpu/x86/lapic.h>
44 #include "option_table.h"
45 #include "pc80/mc146818rtc_early.c"
46 #include "pc80/serial.c"
48 #if CONFIG_USE_INIT == 0
49 #include "lib/memcpy.c"
52 #include "arch/i386/lib/console.c"
55 static void post_code(uint8_t value) {
58 for(i=0;i<0x80000;i++) {
65 #include <cpu/amd/model_fxx_rev.h>
66 #include "northbridge/amd/amdk8/raminit.h"
67 #include "cpu/amd/model_fxx/apic_timer.c"
69 #include "lib/delay.c"
71 //#include "cpu/x86/lapic/boot_cpu.c"
72 #include "northbridge/amd/amdk8/reset_test.c"
74 #include "northbridge/amd/amdk8/debug.c"
76 #include "southbridge/sis/sis966/sis966_early_ctrl.c"
78 #include "northbridge/amd/amdk8/amdk8_f.h"
80 #include "cpu/x86/mtrr.h"
81 #include "cpu/amd/mtrr.h"
82 #include "cpu/x86/tsc.h"
84 #include "northbridge/amd/amdk8/amdk8_f_pci.c"
85 #include "northbridge/amd/amdk8/raminit_f_dqs.c"
87 #include "cpu/amd/dualcore/dualcore.c"
89 void hardwaremain(int ret_addr)
91 struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
92 struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
94 struct node_core_id id;
96 id = get_node_core_id_x();
98 //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
99 print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
101 train_ram(id.nodeid, sysinfo, sysinfox);
104 go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
117 uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
125 void x86_exception(struct eregs *info)