2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 ## This program is free software; you can redistribute it and/or modify
10 ## it under the terms of the GNU General Public License as published by
11 ## the Free Software Foundation; either version 2 of the License, or
12 ## (at your option) any later version.
14 ## This program is distributed in the hope that it will be useful,
15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ## GNU General Public License for more details.
19 ## You should have received a copy of the GNU General Public License
20 ## along with this program; if not, write to the Free Software
21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 uses CONFIG_HAVE_MP_TABLE
26 uses CONFIG_HAVE_PIRQ_TABLE
27 uses CONFIG_HAVE_ACPI_TABLES
28 uses CONFIG_HAVE_ACPI_RESUME
29 uses CONFIG_ACPI_SSDTX_NUM
30 uses CONFIG_USE_FALLBACK_IMAGE
31 uses CONFIG_USE_FAILOVER_IMAGE
32 uses CONFIG_HAVE_FALLBACK_BOOT
33 uses CONFIG_HAVE_FAILOVER_BOOT
34 uses CONFIG_HAVE_HARD_RESET
35 uses CONFIG_IRQ_SLOT_COUNT
36 uses CONFIG_HAVE_OPTION_TABLE
38 uses CONFIG_MAX_PHYSICAL_CPUS
39 uses CONFIG_LOGICAL_CPUS
42 uses CONFIG_FALLBACK_SIZE
43 uses CONFIG_FAILOVER_SIZE
45 uses CONFIG_ROM_SECTION_SIZE
46 uses CONFIG_ROM_IMAGE_SIZE
47 uses CONFIG_ROM_SECTION_SIZE
48 uses CONFIG_ROM_SECTION_OFFSET
49 uses CONFIG_ROM_PAYLOAD
50 uses CONFIG_ROM_PAYLOAD_START
51 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
52 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
53 uses CONFIG_PRECOMPRESSED_PAYLOAD
54 uses CONFIG_PAYLOAD_SIZE
56 uses CONFIG_XIP_ROM_SIZE
57 uses CONFIG_XIP_ROM_BASE
58 uses CONFIG_STACK_SIZE
60 uses CONFIG_USE_OPTION_TABLE
61 uses CONFIG_LB_CKS_RANGE_START
62 uses CONFIG_LB_CKS_RANGE_END
63 uses CONFIG_LB_CKS_LOC
64 uses CONFIG_MAINBOARD_PART_NUMBER
65 uses CONFIG_MAINBOARD_VENDOR
67 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
68 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
69 uses COREBOOT_EXTRA_VERSION
71 uses CONFIG_TTYS0_BAUD
72 uses CONFIG_TTYS0_BASE
74 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
75 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
76 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
77 uses CONFIG_CONSOLE_SERIAL8250
78 uses CONFIG_HAVE_INIT_TIMER
81 uses CONFIG_CROSS_COMPILE
85 uses CONFIG_CONSOLE_VGA
86 uses CONFIG_USBDEBUG_DIRECT
87 uses CONFIG_PCI_ROM_RUN
88 uses CONFIG_HW_MEM_HOLE_SIZEK
89 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
90 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
92 uses CONFIG_HT_CHAIN_UNITID_BASE
93 uses CONFIG_HT_CHAIN_END_UNITID_BASE
94 uses CONFIG_SB_HT_CHAIN_ON_BUS0
95 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
97 uses CONFIG_USE_DCACHE_RAM
98 uses CONFIG_DCACHE_RAM_BASE
99 uses CONFIG_DCACHE_RAM_SIZE
100 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
103 uses CONFIG_SERIAL_CPU_INIT
105 uses CONFIG_ENABLE_APIC_EXT_ID
106 uses CONFIG_APIC_ID_OFFSET
107 uses CONFIG_LIFT_BSP_APIC_ID
109 uses CONFIG_PCI_64BIT_PREF_MEM
111 uses CONFIG_LB_MEM_TOPK
113 uses CONFIG_AP_CODE_IN_CAR
115 uses CONFIG_MEM_TRAIN_SEQ
117 uses CONFIG_WAIT_BEFORE_CPUS_INIT
119 uses CONFIG_USE_PRINTK_IN_CAR
126 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
128 default CONFIG_ROM_SIZE=524288
129 #default CONFIG_ROM_SIZE=0x100000
132 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
136 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
138 default CONFIG_FAILOVER_SIZE=0x01000
141 default CONFIG_LB_MEM_TOPK=2048
144 ## Build code for the fallback boot
146 default CONFIG_HAVE_FALLBACK_BOOT=1
147 default CONFIG_HAVE_FAILOVER_BOOT=1
150 ## Build code to reset the motherboard from coreboot
152 default CONFIG_HAVE_HARD_RESET=1
155 ## Build code to export a programmable irq routing table
157 default CONFIG_HAVE_PIRQ_TABLE=1
158 default CONFIG_IRQ_SLOT_COUNT=11
161 ## Build code to export an x86 MP table
162 ## Useful for specifying IRQ routing values
164 default CONFIG_HAVE_MP_TABLE=0
166 ## ACPI tables will be included
167 default CONFIG_HAVE_ACPI_TABLES=0
170 ## Build code to export a CMOS option table
172 default CONFIG_HAVE_OPTION_TABLE=1
175 ## Move the default coreboot cmos range off of AMD RTC registers
177 default CONFIG_LB_CKS_RANGE_START=49
178 default CONFIG_LB_CKS_RANGE_END=122
179 default CONFIG_LB_CKS_LOC=123
182 ## Build code for SMP support
183 ## Only worry about 2 micro processors
186 default CONFIG_MAX_CPUS=2
187 default CONFIG_MAX_PHYSICAL_CPUS=1
188 default CONFIG_LOGICAL_CPUS=1
190 #default CONFIG_SERIAL_CPU_INIT=0
192 default CONFIG_ENABLE_APIC_EXT_ID=0
193 default CONFIG_APIC_ID_OFFSET=0x10
194 default CONFIG_LIFT_BSP_APIC_ID=1
196 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
198 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
200 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
202 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
204 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
205 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
207 #Opteron K8 1G HT Support
208 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
211 default CONFIG_CONSOLE_VGA=1
212 default CONFIG_PCI_ROM_RUN=1
214 #default CONFIG_USBDEBUG_DIRECT=0
216 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
217 default CONFIG_HT_CHAIN_UNITID_BASE=0
219 #real SB Unit ID, default is 0x20, mean dont touch it at last
220 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
222 #make the SB HT chain on bus 0, default is not (0)
223 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
225 #only offset for SB chain?, default is yes(1)
226 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
228 #allow capable device use that above 4G
229 #default CONFIG_PCI_64BIT_PREF_MEM=1
232 ## enable CACHE_AS_RAM specifics
234 default CONFIG_USE_DCACHE_RAM=1
235 default CONFIG_DCACHE_RAM_BASE=0xc8000
236 default CONFIG_DCACHE_RAM_SIZE=0x08000
237 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
238 default CONFIG_USE_INIT=0
240 default CONFIG_AP_CODE_IN_CAR=0
241 default CONFIG_MEM_TRAIN_SEQ=2
242 default CONFIG_WAIT_BEFORE_CPUS_INIT=0
245 ## Build code to setup a generic IOAPIC
247 default CONFIG_IOAPIC=1
250 ## Clean up the motherboard id strings
252 default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk"
253 default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
254 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
255 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
258 ### coreboot layout values
261 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
262 default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
265 ## Use a small 8K stack
267 default CONFIG_STACK_SIZE=0x2000
270 ## Use a small 32K heap
272 default CONFIG_HEAP_SIZE=0x8000
275 ## Only use the option table in a normal image
277 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
280 ## Coreboot C code runs at this location in RAM
282 default CONFIG_RAMBASE=0x00100000
285 ## Load the payload from the ROM
287 default CONFIG_ROM_PAYLOAD = 1
289 #default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
292 ### Defaults of options that you may want to override in the target config file
296 ## The default compiler
298 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
302 ## Disable the gdb stub by default
304 default CONFIG_GDB_STUB=0
307 ## The Serial Console
309 default CONFIG_USE_PRINTK_IN_CAR=1
311 # To Enable the Serial Console
312 default CONFIG_CONSOLE_SERIAL8250=1
314 ## Select the serial console baud rate
315 default CONFIG_TTYS0_BAUD=115200
316 #default CONFIG_TTYS0_BAUD=57600
317 #default CONFIG_TTYS0_BAUD=38400
318 #default CONFIG_TTYS0_BAUD=19200
319 #default CONFIG_TTYS0_BAUD=9600
320 #default CONFIG_TTYS0_BAUD=4800
321 #default CONFIG_TTYS0_BAUD=2400
322 #default CONFIG_TTYS0_BAUD=1200
324 # Select the serial console base port
325 default CONFIG_TTYS0_BASE=0x3f8
327 # Select the serial protocol
328 # This defaults to 8 data bits, 1 stop bit, and no parity
329 default CONFIG_TTYS0_LCS=0x3
332 ### Select the coreboot loglevel
334 ## EMERG 1 system is unusable
335 ## ALERT 2 action must be taken immediately
336 ## CRIT 3 critical conditions
337 ## ERR 4 error conditions
338 ## WARNING 5 warning conditions
339 ## NOTICE 6 normal but significant condition
340 ## INFO 7 informational
341 ## CONFIG_DEBUG 8 debug-level messages
342 ## SPEW 9 Way too many details
344 ## Request this level of debugging output
345 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
346 ## At a maximum only compile in this level of debugging
347 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
350 ## Select power on after power fail setting
351 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
358 default CONFIG_CBFS=1