src/mainboard/gigabyte/ga_2761gxdk/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   8 ##
   9 ## This program is free software; you can redistribute it and/or modify
  10 ## it under the terms of the GNU General Public License as published by
  11 ## the Free Software Foundation; either version 2 of the License, or
  12 ## (at your option) any later version.
  13 ##
  14 ## This program is distributed in the hope that it will be useful,
  15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ## GNU General Public License for more details.
  18 ##
  19 ## You should have received a copy of the GNU General Public License
  20 ## along with this program; if not, write to the Free Software
  21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 ##
  23
  24 ##
  25 ## Compute the location and size of where this firmware image
  26 ## (coreboot plus bootloader) will live in the boot rom chip.
  27 ##
  28 if USE_FAILOVER_IMAGE
  29         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  30         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  31 else
  32     if USE_FALLBACK_IMAGE
  33         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  34         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35     else
  36         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  37         default ROM_SECTION_OFFSET = 0
  38     end
  39 end
  40
  41 ##
  42 ## Compute the start location and size size of
  43 ## The coreboot bootloader.
  44 ##
  45 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  46 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  47
  48 ##
  49 ## Compute where this copy of coreboot will start in the boot rom
  50 ##
  51 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  52
  53 ##
  54 ## Compute a range of ROM that can cached to speed up coreboot,
  55 ## execution speed.
  56 ##
  57 ## XIP_ROM_SIZE must be a power of 2.
  58 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  59 ##
  60 default XIP_ROM_SIZE=65536
  61
  62 if USE_FAILOVER_IMAGE
  63         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  64 else
  65     if USE_FALLBACK_IMAGE
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  67     else
  68         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  69     end
  70 end
  71
  72 arch i386 end
  73
  74 ##
  75 ## Build the objects we have code for in this directory.
  76 ##
  77
  78 driver mainboard.o
  79 #needed by irq_tables and mptable and acpi_tables
  80 object get_bus_conf.o
  81
  82 if HAVE_MP_TABLE object mptable.o end
  83 if HAVE_PIRQ_TABLE object irq_tables.o end
  84 #object reset.o
  85 if USE_DCACHE_RAM
  86
  87         if CONFIG_USE_INIT
  88                 makerule ./cache_as_ram_auto.o
  89                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  90                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  91                 end
  92         else
  93                 makerule ./cache_as_ram_auto.inc
  94                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  95                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -g -dA -fverbose-asm -Wall -c -S -o $@"
  96                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  97                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  98                 end
  99         end
 100
 101 end
 102
 103 if USE_FAILOVER_IMAGE
 104 else
 105     if CONFIG_AP_CODE_IN_CAR
 106         makerule ./apc_auto.o
 107                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 108                 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 109         end
 110         ldscript /arch/i386/init/ldscript_apc.lb
 111     end
 112 end
 113
 114
 115 ##
 116 ## Build our 16 bit and 32 bit coreboot entry code
 117 ##
 118 if HAVE_FAILOVER_BOOT
 119     if USE_FAILOVER_IMAGE
 120         mainboardinit cpu/x86/16bit/entry16.inc
 121         ldscript /cpu/x86/16bit/entry16.lds
 122     end
 123 else
 124     if USE_FALLBACK_IMAGE
 125         mainboardinit cpu/x86/16bit/entry16.inc
 126         ldscript /cpu/x86/16bit/entry16.lds
 127     end
 128 end
 129
 130 mainboardinit cpu/x86/32bit/entry32.inc
 131
 132 if USE_DCACHE_RAM
 133         if CONFIG_USE_INIT
 134                 ldscript /cpu/x86/32bit/entry32.lds
 135         end
 136
 137         if CONFIG_USE_INIT
 138                 ldscript /cpu/amd/car/cache_as_ram.lds
 139         end
 140 end
 141
 142
 143 ##
 144 ## Build our reset vector (This is where coreboot is entered)
 145 ##
 146 if HAVE_FAILOVER_BOOT
 147     if USE_FAILOVER_IMAGE
 148         mainboardinit cpu/x86/16bit/reset16.inc
 149         ldscript /cpu/x86/16bit/reset16.lds
 150     else
 151         mainboardinit cpu/x86/32bit/reset32.inc
 152         ldscript /cpu/x86/32bit/reset32.lds
 153     end
 154 else
 155     if USE_FALLBACK_IMAGE
 156         mainboardinit cpu/x86/16bit/reset16.inc
 157         ldscript /cpu/x86/16bit/reset16.lds
 158     else
 159         mainboardinit cpu/x86/32bit/reset32.inc
 160         ldscript /cpu/x86/32bit/reset32.lds
 161     end
 162 end
 163
 164 ##
 165 ## Include an id string (For safe flashing)
 166 ##
 167 mainboardinit southbridge/sis/sis966/id.inc
 168 ldscript /southbridge/sis/sis966/id.lds
 169
 170 ##
 171 ## ROMSTRAP table for MCP55
 172 ##
 173 if HAVE_FAILOVER_BOOT
 174     if USE_FAILOVER_IMAGE
 175         mainboardinit southbridge/sis/sis966/romstrap.inc
 176         ldscript /southbridge/sis/sis966/romstrap.lds
 177     end
 178 else
 179     if USE_FALLBACK_IMAGE
 180         mainboardinit southbridge/sis/sis966/romstrap.inc
 181         ldscript /southbridge/sis/sis966/romstrap.lds
 182     end
 183 end
 184
 185 if USE_DCACHE_RAM
 186         ##
 187         ## Setup Cache-As-Ram
 188         ##
 189         mainboardinit cpu/amd/car/cache_as_ram.inc
 190 end
 191
 192 ###
 193 ### This is the early phase of coreboot startup
 194 ### Things are delicate and we test to see if we should
 195 ### failover to another image.
 196 ###
 197 if HAVE_FAILOVER_BOOT
 198     if USE_FAILOVER_IMAGE
 199         if USE_DCACHE_RAM
 200                 ldscript /arch/i386/lib/failover_failover.lds
 201         end
 202     end
 203 else
 204     if USE_FALLBACK_IMAGE
 205         if USE_DCACHE_RAM
 206                 ldscript /arch/i386/lib/failover.lds
 207         end
 208     end
 209 end
 210
 211 ##
 212 ## Setup RAM
 213 ##
 214 if USE_DCACHE_RAM
 215
 216         if CONFIG_USE_INIT
 217                 initobject cache_as_ram_auto.o
 218         else
 219                 mainboardinit ./cache_as_ram_auto.inc
 220         end
 221 end
 222
 223 ##
 224 ## Include the secondary Configuration files
 225 ##
 226 if CONFIG_CHIP_NAME
 227         config chip.h
 228 end
 229
 230 chip northbridge/amd/amdk8/root_complex
 231         device apic_cluster 0 on
 232                 chip cpu/amd/socket_AM2
 233                         device apic 0 on end
 234                 end
 235         end
 236         device pci_domain 0 on
 237                 chip northbridge/amd/amdk8 #mc0
 238                         device pci 18.0 on
 239                                 #  devices on link 0, link 0 == LDT 0
 240                                 chip southbridge/sis/sis966
 241                                         device pci 0.0 on end   # Northbridge
 242                                         device pci 1.0 on               # AGP bridge
 243                                           chip drivers/pci/onboard      # Integrated VGA
 244                                                 device pci 0.0 on end
 245                                                 register "rom_address" = "0xfff80000"
 246                                           end
 247                                         end
 248                                         device pci 2.0 on # LPC
 249                                                 chip superio/ite/it8716f
 250                                                         device pnp 2e.0 off #  Floppy (N/A)
 251                                                                 io 0x60 = 0x3f0
 252                                                                 irq 0x70 = 6
 253                                                                 drq 0x74 = 2
 254                                                         end
 255                                                         device pnp 2e.1 on #  Com1
 256                                                                 io 0x60 = 0x3f8
 257                                                                 irq 0x70 = 4
 258                                                         end
 259                                                         device pnp 2e.2 off #  Com2 (N/A)
 260                                                                 io 0x60 = 0x2f8
 261                                                                 irq 0x70 = 3
 262                                                         end
 263                                                         device pnp 2e.3 off #  Parallel port (N/A)
 264                                                                 io 0x60 = 0x378
 265                                                                 irq 0x70 = 7
 266                                                         end
 267                                                         device pnp 2e.4 on #  EC
 268                                                                 io 0x60 = 0x290
 269                                                                 io 0x62 = 0x230
 270                                                                 irq 0x70 = 9
 271                                                         end
 272                                                         device pnp 2e.5 off #  PS/2 keyboard (N/A)
 273                                                                 io 0x60 = 0x60
 274                                                                 io 0x62 = 0x64
 275                                                                 irq 0x70 = 1
 276                                                         end
 277                                                         device pnp 2e.6 off #  Mouse (N/A)
 278                                                                 irq 0x70 = 12
 279                                                         end
 280                                                         device pnp 2e.8 off #  MIDI (N/A)
 281                                                                 io 0x60 = 0x300
 282                                                                 irq 0x70 = 10
 283                                                         end
 284                                                         device pnp 2e.9 off #  GAME (N/A)
 285                                                                 io 0x60 = 0x220
 286                                                         end
 287                                                         device pnp 2e.a off end #  CIR (N/A)
 288                                                 end
 289                                         end
 290
 291                                         device pci 2.5 off end # IDE (SiS5513)
 292                                         device pci 2.6 off end # Modem (SiS7013)
 293                                         device pci 2.7 off end # Audio (SiS7012)
 294                                         device pci 3.0 on end # USB (SiS7001,USB1.1)
 295                                         device pci 3.1 on end # USB (SiS7001,USB1.1)
 296                                         device pci 3.3 on end # USB (SiS7002,USB2.0)
 297                                         device pci 4.0 on end # NIC (SiS191)
 298                                         device pci 5.0 on end # SATA (SiS1183,Native Mode)
 299                                         device pci 6.0 on end # PCI-e x1
 300                                         device pci 7.0 on end # PCI-e x1
 301                                         device pci a.0 off end
 302                                         device pci b.0 off end
 303                                         device pci c.0 off end
 304                                         device pci d.0 off end
 305                                         device pci e.0 off end
 306                                         device pci f.0 off end # HD Audio (SiS7502)
 307
 308                                         register "ide0_enable" = "1"
 309                                         register "ide1_enable" = "1"
 310                                         register "sata0_enable" = "1"
 311                                         register "sata1_enable" = "1"
 312                                 end
 313                         end #  device pci 18.0
 314                         device pci 18.0 on end # Link 1
 315                         device pci 18.0 on end
 316                         device pci 18.1 on end
 317                         device pci 18.2 on end
 318                         device pci 18.3 on end
 319                 end # mc0
 320
 321         end # PCI domain
 322
 323 #       chip drivers/generic/debug
 324 #               device pnp 0.0 off end # chip name
 325 #               device pnp 0.1 on end # pci_regs_all
 326 #               device pnp 0.2 off end # mem
 327 #               device pnp 0.3 off end # cpuid
 328 #               device pnp 0.4 off end # smbus_regs_all
 329 #               device pnp 0.5 off end # dual core msr
 330 #               device pnp 0.6 off end # cache size
 331 #               device pnp 0.7 off end # tsc
 332 #               device pnp 0.8 off end # io
 333 #               device pnp 0.9 off end # io
 334 #       end
 335 end #root_complex