src/mainboard/gigabyte/ga_2761gxdk/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   8 ##
   9 ## This program is free software; you can redistribute it and/or modify
  10 ## it under the terms of the GNU General Public License as published by
  11 ## the Free Software Foundation; either version 2 of the License, or
  12 ## (at your option) any later version.
  13 ##
  14 ## This program is distributed in the hope that it will be useful,
  15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ## GNU General Public License for more details.
  18 ##
  19 ## You should have received a copy of the GNU General Public License
  20 ## along with this program; if not, write to the Free Software
  21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 ##
  23
  24 ##
  25 ## Compute the location and size of where this firmware image
  26 ## (coreboot plus bootloader) will live in the boot rom chip.
  27 ##
  28 if USE_FAILOVER_IMAGE
  29         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  30         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  31 else
  32     if USE_FALLBACK_IMAGE
  33         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  34         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35     else
  36         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  37         default ROM_SECTION_OFFSET = 0
  38     end
  39 end
  40
  41 ##
  42 ## Compute the start location and size size of
  43 ## The coreboot bootloader.
  44 ##
  45 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  46 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  47
  48 ##
  49 ## Compute where this copy of coreboot will start in the boot rom
  50 ##
  51 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  52
  53 ##
  54 ## Compute a range of ROM that can cached to speed up coreboot,
  55 ## execution speed.
  56 ##
  57 ## XIP_ROM_SIZE must be a power of 2.
  58 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  59 ##
  60 default XIP_ROM_SIZE=65536
  61
  62 if USE_FAILOVER_IMAGE
  63         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  64 else
  65     if USE_FALLBACK_IMAGE
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  67     else
  68         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  69     end
  70 end
  71
  72 arch i386 end
  73
  74 ##
  75 ## Build the objects we have code for in this directory.
  76 ##
  77
  78 driver mainboard.o
  79 #needed by irq_tables and mptable and acpi_tables
  80 object get_bus_conf.o
  81
  82 if HAVE_MP_TABLE object mptable.o end
  83 if HAVE_PIRQ_TABLE object irq_tables.o end
  84 #object reset.o
  85
  86         if CONFIG_USE_INIT
  87                 makerule ./cache_as_ram_auto.o
  88                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  89                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  90                 end
  91         else
  92                 makerule ./cache_as_ram_auto.inc
  93                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  94                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  95                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  96                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  97                 end
  98         end
  99
 100 if USE_FAILOVER_IMAGE
 101 else
 102     if CONFIG_AP_CODE_IN_CAR
 103         makerule ./apc_auto.o
 104                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 105                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
 106         end
 107         ldscript /arch/i386/init/ldscript_apc.lb
 108     end
 109 end
 110
 111
 112 ##
 113 ## Build our 16 bit and 32 bit coreboot entry code
 114 ##
 115 if HAVE_FAILOVER_BOOT
 116     if USE_FAILOVER_IMAGE
 117         mainboardinit cpu/x86/16bit/entry16.inc
 118         ldscript /cpu/x86/16bit/entry16.lds
 119     end
 120 else
 121     if USE_FALLBACK_IMAGE
 122         mainboardinit cpu/x86/16bit/entry16.inc
 123         ldscript /cpu/x86/16bit/entry16.lds
 124     end
 125 end
 126
 127 mainboardinit cpu/x86/32bit/entry32.inc
 128
 129         if CONFIG_USE_INIT
 130                 ldscript /cpu/x86/32bit/entry32.lds
 131         end
 132
 133         if CONFIG_USE_INIT
 134                 ldscript /cpu/amd/car/cache_as_ram.lds
 135         end
 136
 137 ##
 138 ## Build our reset vector (This is where coreboot is entered)
 139 ##
 140 if HAVE_FAILOVER_BOOT
 141     if USE_FAILOVER_IMAGE
 142         mainboardinit cpu/x86/16bit/reset16.inc
 143         ldscript /cpu/x86/16bit/reset16.lds
 144     else
 145         mainboardinit cpu/x86/32bit/reset32.inc
 146         ldscript /cpu/x86/32bit/reset32.lds
 147     end
 148 else
 149     if USE_FALLBACK_IMAGE
 150         mainboardinit cpu/x86/16bit/reset16.inc
 151         ldscript /cpu/x86/16bit/reset16.lds
 152     else
 153         mainboardinit cpu/x86/32bit/reset32.inc
 154         ldscript /cpu/x86/32bit/reset32.lds
 155     end
 156 end
 157
 158 ##
 159 ## Include an id string (For safe flashing)
 160 ##
 161 mainboardinit southbridge/sis/sis966/id.inc
 162 ldscript /southbridge/sis/sis966/id.lds
 163
 164 ##
 165 ## ROMSTRAP table for MCP55
 166 ##
 167 if HAVE_FAILOVER_BOOT
 168     if USE_FAILOVER_IMAGE
 169         mainboardinit southbridge/sis/sis966/romstrap.inc
 170         ldscript /southbridge/sis/sis966/romstrap.lds
 171     end
 172 else
 173     if USE_FALLBACK_IMAGE
 174         mainboardinit southbridge/sis/sis966/romstrap.inc
 175         ldscript /southbridge/sis/sis966/romstrap.lds
 176     end
 177 end
 178
 179         ##
 180         ## Setup Cache-As-Ram
 181         ##
 182         mainboardinit cpu/amd/car/cache_as_ram.inc
 183
 184 ###
 185 ### This is the early phase of coreboot startup
 186 ### Things are delicate and we test to see if we should
 187 ### failover to another image.
 188 ###
 189 if HAVE_FAILOVER_BOOT
 190     if USE_FAILOVER_IMAGE
 191                 ldscript /arch/i386/lib/failover_failover.lds
 192     end
 193 else
 194     if USE_FALLBACK_IMAGE
 195                 ldscript /arch/i386/lib/failover.lds
 196     end
 197 end
 198
 199 ##
 200 ## Setup RAM
 201 ##
 202         if CONFIG_USE_INIT
 203                 initobject cache_as_ram_auto.o
 204         else
 205                 mainboardinit ./cache_as_ram_auto.inc
 206         end
 207
 208 ##
 209 ## Include the secondary Configuration files
 210 ##
 211 config chip.h
 212
 213 chip northbridge/amd/amdk8/root_complex
 214         device apic_cluster 0 on
 215                 chip cpu/amd/socket_AM2
 216                         device apic 0 on end
 217                 end
 218         end
 219         device pci_domain 0 on
 220                 chip northbridge/amd/amdk8 #mc0
 221                         device pci 18.0 on
 222                                 #  devices on link 0, link 0 == LDT 0
 223                                 chip southbridge/sis/sis966
 224                                         device pci 0.0 on end   # Northbridge
 225                                         device pci 1.0 on               # AGP bridge
 226                                           chip drivers/pci/onboard      # Integrated VGA
 227                                                 device pci 0.0 on end
 228                                                 register "rom_address" = "0xfff80000"
 229                                           end
 230                                         end
 231                                         device pci 2.0 on # LPC
 232                                                 chip superio/ite/it8716f
 233                                                         device pnp 2e.0 off #  Floppy (N/A)
 234                                                                 io 0x60 = 0x3f0
 235                                                                 irq 0x70 = 6
 236                                                                 drq 0x74 = 2
 237                                                         end
 238                                                         device pnp 2e.1 on #  Com1
 239                                                                 io 0x60 = 0x3f8
 240                                                                 irq 0x70 = 4
 241                                                         end
 242                                                         device pnp 2e.2 off #  Com2 (N/A)
 243                                                                 io 0x60 = 0x2f8
 244                                                                 irq 0x70 = 3
 245                                                         end
 246                                                         device pnp 2e.3 off #  Parallel port (N/A)
 247                                                                 io 0x60 = 0x378
 248                                                                 irq 0x70 = 7
 249                                                         end
 250                                                         device pnp 2e.4 on #  EC
 251                                                                 io 0x60 = 0x290
 252                                                                 io 0x62 = 0x230
 253                                                                 irq 0x70 = 9
 254                                                         end
 255                                                         device pnp 2e.5 off #  PS/2 keyboard (N/A)
 256                                                                 io 0x60 = 0x60
 257                                                                 io 0x62 = 0x64
 258                                                                 irq 0x70 = 1
 259                                                         end
 260                                                         device pnp 2e.6 off #  Mouse (N/A)
 261                                                                 irq 0x70 = 12
 262                                                         end
 263                                                         device pnp 2e.8 off #  MIDI (N/A)
 264                                                                 io 0x60 = 0x300
 265                                                                 irq 0x70 = 10
 266                                                         end
 267                                                         device pnp 2e.9 off #  GAME (N/A)
 268                                                                 io 0x60 = 0x220
 269                                                         end
 270                                                         device pnp 2e.a off end #  CIR (N/A)
 271                                                 end
 272                                         end
 273
 274                                         device pci 2.5 off end # IDE (SiS5513)
 275                                         device pci 2.6 off end # Modem (SiS7013)
 276                                         device pci 2.7 off end # Audio (SiS7012)
 277                                         device pci 3.0 on end # USB (SiS7001,USB1.1)
 278                                         device pci 3.1 on end # USB (SiS7001,USB1.1)
 279                                         device pci 3.3 on end # USB (SiS7002,USB2.0)
 280                                         device pci 4.0 on end # NIC (SiS191)
 281                                         device pci 5.0 on end # SATA (SiS1183,Native Mode)
 282                                         device pci 6.0 on end # PCI-e x1
 283                                         device pci 7.0 on end # PCI-e x1
 284                                         device pci a.0 off end
 285                                         device pci b.0 off end
 286                                         device pci c.0 off end
 287                                         device pci d.0 off end
 288                                         device pci e.0 off end
 289                                         device pci f.0 off end # HD Audio (SiS7502)
 290
 291                                         register "ide0_enable" = "1"
 292                                         register "ide1_enable" = "1"
 293                                         register "sata0_enable" = "1"
 294                                         register "sata1_enable" = "1"
 295                                 end
 296                         end #  device pci 18.0
 297                         device pci 18.0 on end # Link 1
 298                         device pci 18.0 on end
 299                         device pci 18.1 on end
 300                         device pci 18.2 on end
 301                         device pci 18.3 on end
 302                 end # mc0
 303
 304         end # PCI domain
 305
 306 #       chip drivers/generic/debug
 307 #               device pnp 0.0 off end # chip name
 308 #               device pnp 0.1 on end # pci_regs_all
 309 #               device pnp 0.2 off end # mem
 310 #               device pnp 0.3 off end # cpuid
 311 #               device pnp 0.4 off end # smbus_regs_all
 312 #               device pnp 0.5 off end # dual core msr
 313 #               device pnp 0.6 off end # cache size
 314 #               device pnp 0.7 off end # tsc
 315 #               device pnp 0.8 off end # io
 316 #               device pnp 0.9 off end # io
 317 #       end
 318 end #root_complex