1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
12 #if CONFIG_WRITE_HIGH_TABLES==1
13 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
14 extern uint64_t high_tables_base, high_tables_size;
17 #define CMOS_ADDR_PORT 0x70
18 #define CMOS_DATA_PORT 0x71
19 #define HIGH_RAM_ADDR 0x35
20 #define LOW_RAM_ADDR 0x34
22 static void cpu_pci_domain_set_resources(device_t dev)
24 u32 pci_tolm = find_pci_tolm(dev->link_list);
25 unsigned long tomk = 0, tolmk;
28 outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT);
29 tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
30 outb (LOW_RAM_ADDR, CMOS_ADDR_PORT);
31 tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
34 printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
37 /* Compute the top of Low memory */
38 tolmk = pci_tolm >> 10;
40 /* The PCI hole does not overlap the memory. */
44 /* Report the memory regions. */
46 ram_resource(dev, idx++, 0, 640);
47 ram_resource(dev, idx++, 768, tolmk - 768);
49 #if CONFIG_WRITE_HIGH_TABLES==1
50 /* Leave some space for ACPI, PIRQ and MP tables */
51 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
52 high_tables_size = HIGH_TABLES_SIZE * 1024;
55 assign_resources(dev->link_list);
58 static void cpu_pci_domain_read_resources(struct device *dev)
62 pci_domain_read_resources(dev);
64 /* Reserve space for the IOAPIC. This should be in the Southbridge,
65 * but I couldn't tell which device to put it in. */
66 res = new_resource(dev, 2);
67 res->base = 0xfec00000UL;
68 res->size = 0x100000UL;
69 res->limit = 0xffffffffUL;
70 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
73 /* Reserve space for the LAPIC. There's one in every processor, but
74 * the space only needs to be reserved once, so we do it here. */
75 res = new_resource(dev, 3);
76 res->base = 0xfee00000UL;
77 res->size = 0x10000UL;
78 res->limit = 0xffffffffUL;
79 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
83 static struct device_operations pci_domain_ops = {
84 .read_resources = cpu_pci_domain_read_resources,
85 .set_resources = cpu_pci_domain_set_resources,
86 .enable_resources = NULL,
88 .scan_bus = pci_domain_scan_bus,
91 static void enable_dev(struct device *dev)
93 /* Set the operations if it is a special bus type */
94 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
95 dev->ops = &pci_domain_ops;
100 struct chip_operations mainboard_emulation_qemu_x86_ops = {
101 CHIP_NAME("QEMU Northbridge")
102 .enable_dev = enable_dev,