2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
5 default ROM_SIZE = 256 * 1024
6 default ROM_SECTION_SIZE = ROM_SIZE
7 default ROM_SECTION_OFFSET = 0
10 ## Compute the start location and size size of
11 ## The coreboot bootloader.
13 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
14 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
17 ## Compute where this copy of coreboot will start in the boot rom
19 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
22 ## Compute a range of ROM that can cached to speed up coreboot,
25 ## XIP_ROM_SIZE must be a power of 2.
26 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
28 default XIP_ROM_SIZE=32*1024
29 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
32 ## Set all of the defaults for an x86 architecture
38 ## Build the objects we have code for in this directory.
42 if HAVE_PIRQ_TABLE object irq_tables.o end
49 depends "$(MAINBOARD)/failover.c ../romcc"
50 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
53 makerule ./failover.inc
54 depends "$(MAINBOARD)/failover.c ../romcc"
55 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
59 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
60 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
63 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
64 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
68 ## Build our 16 bit and 32 bit coreboot entry code
70 mainboardinit cpu/x86/16bit/entry16.inc
71 mainboardinit cpu/x86/32bit/entry32.inc
72 ldscript /cpu/x86/16bit/entry16.lds
73 ldscript /cpu/x86/32bit/entry32.lds
76 ## Build our reset vector (This is where coreboot is entered)
78 mainboardinit cpu/x86/16bit/reset16.inc
79 ldscript /cpu/x86/16bit/reset16.lds
81 ### Should this be in the northbridge code?
82 mainboardinit arch/i386/lib/cpu_reset.inc
85 ## Include an id string (For safe flashing)
87 mainboardinit arch/i386/lib/id.inc
88 ldscript /arch/i386/lib/id.lds
91 ### O.k. We aren't just an intermediary anymore!
97 mainboardinit cpu/x86/fpu/enable_fpu.inc
98 mainboardinit ./auto.inc
101 ## Include the secondary Configuration files
106 chip cpu/emulation/qemu-x86
107 device pci_domain 0 on
108 device pci 0.0 on end
110 chip southbridge/intel/i82371eb # southbridge
111 device pci 01.0 on end
112 device pci 01.1 on end
113 register "ide0_enable" = "1"
114 register "ide1_enable" = "1"
117 # register "com1" = "{1}"
118 # register "com1" = "{1, 0, 0x3f8, 4}"