src/mainboard/eaglelion/5bcm/romstage.c

   1 #define ASSEMBLY 1
   2
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <arch/hlt.h>
  10 #include <stdlib.h>
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "lib/ramtest.c"
  14 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
  15 #include "superio/nsc/pc97317/pc97317_early_serial.c"
  16 //#include "northbridge/intel/i440bx/raminit.h"
  17 #include "cpu/x86/bist.h"
  18 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
  19
  20 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
  21
  22 //#include "lib/delay.c"
  23
  24 #include "northbridge/amd/gx1/raminit.c"
  25
  26 static void main(unsigned long bist)
  27 {
  28         pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  29         uart_init();
  30         console_init();
  31
  32         /* Halt if there was a built in self test failure */
  33         report_bist_failure(bist);
  34
  35         cs5530_enable_rom();
  36
  37         sdram_init();
  38
  39         /* Check all of memory */
  40 #if 0
  41         ram_check(0x00000000, msr.lo);
  42 #endif
  43 #if 0
  44         static const struct {
  45                 unsigned long lo, hi;
  46         } check_addrs[] = {
  47                 /* Check 16MB of memory @ 0*/
  48                 { 0x00000000, 0x01000000 },
  49 #if TOTAL_CPUS > 1
  50                 /* Check 16MB of memory @ 2GB */
  51                 { 0x80000000, 0x81000000 },
  52 #endif
  53         };
  54         int i;
  55         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
  56                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
  57         }
  58 #endif
  59 }