1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
17 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
24 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
25 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
28 makerule ./failover.inc
29 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
30 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
34 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
35 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
38 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
39 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
43 ## Build our 16 bit and 32 bit coreboot entry code
45 mainboardinit cpu/x86/16bit/entry16.inc
46 mainboardinit cpu/x86/32bit/entry32.inc
47 ldscript /cpu/x86/16bit/entry16.lds
48 ldscript /cpu/x86/32bit/entry32.lds
51 ## Build our reset vector (This is where coreboot is entered)
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/reset16.inc
55 ldscript /cpu/x86/16bit/reset16.lds
57 mainboardinit cpu/x86/32bit/reset32.inc
58 ldscript /cpu/x86/32bit/reset32.lds
61 ### Should this be in the northbridge code?
62 mainboardinit arch/i386/lib/cpu_reset.inc
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
71 ### This is the early phase of coreboot startup
72 ### Things are delicate and we test to see if we should
73 ### failover to another image.
75 if CONFIG_USE_FALLBACK_IMAGE
76 ldscript /arch/i386/lib/failover.lds
77 mainboardinit ./failover.inc
81 ### O.k. We aren't just an intermediary anymore!
87 mainboardinit cpu/x86/fpu/enable_fpu.inc
88 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
89 mainboardinit cpu/amd/model_gx1/gx_setup.inc
90 mainboardinit ./auto.inc
93 ## Include the secondary Configuration files
98 chip northbridge/amd/gx1
99 device pci_domain 0 on
100 device pci 0.0 on end
101 chip southbridge/amd/cs5530
103 chip superio/nsc/pc97317
104 device pnp 2e.0 on # Keyboard
109 device pnp 2e.1 on # Mouse
112 device pnp 2e.2 on # RTC
116 device pnp 2e.3 off # FDC
118 device pnp 2e.4 on # Parallel Port
122 device pnp 2e.5 on # COM2
126 device pnp 2e.6 on # COM1
130 device pnp 2e.7 on # GPIO
133 device pnp 2e.8 on # Power Management
136 register "com1" = "{115200}"
137 register "com2" = "{38400}"
139 device pci 12.1 off end # SMI
140 device pci 12.2 on end # IDE
141 device pci 12.3 off end # Audio
142 device pci 12.4 off end # VGA
147 chip cpu/amd/model_gx1