4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_ROM_PAYLOAD
13 uses MAINBOARD_PART_NUMBER
14 uses COREBOOT_EXTRA_VERSION
23 uses ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
26 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
27 uses CONFIG_PRECOMPRESSED_PAYLOAD
38 uses DEFAULT_CONSOLE_LOGLEVEL
39 uses MAXIMUM_CONSOLE_LOGLEVEL
40 uses CONFIG_CONSOLE_SERIAL8250
44 uses CONFIG_UDELAY_TSC
45 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
46 uses CONFIG_CONSOLE_VGA
47 uses CONFIG_PCI_ROM_RUN
54 ## ROM_SIZE is the size of boot ROM that this board will use.
55 default ROM_SIZE = 256*1024
60 default CONFIG_CONSOLE_VGA=0
61 default CONFIG_VIDEO_MB=8
62 default CONFIG_PCI_ROM_RUN=0
65 ## Build code for the fallback boot
67 default HAVE_FALLBACK_BOOT=1
72 default HAVE_MP_TABLE=0
75 ## Build code to reset the motherboard from coreboot
77 default HAVE_HARD_RESET=0
79 ## Delay timer options
81 default CONFIG_UDELAY_TSC=1
82 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
85 ## Build code to export a programmable irq routing table
87 default HAVE_PIRQ_TABLE=1
88 default IRQ_SLOT_COUNT=6
93 ## Build code to export a CMOS option table
95 default HAVE_OPTION_TABLE=0
98 ### coreboot layout values
101 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
102 default ROM_IMAGE_SIZE = 65536
103 default FALLBACK_SIZE = 131072
106 ## enable CACHE_AS_RAM specifics
108 default USE_DCACHE_RAM=1
109 default DCACHE_RAM_BASE=0xc8000
110 default DCACHE_RAM_SIZE=0x08000
113 ## Use a small 8K stack
115 default STACK_SIZE=0x2000
118 ## Use a small 16K heap
120 default HEAP_SIZE=0x4000
123 ## Only use the option table in a normal image
125 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
126 default USE_OPTION_TABLE = 0
128 default _RAMBASE = 0x00004000
130 default CONFIG_ROM_PAYLOAD = 1
133 ## The default compiler
135 default CROSS_COMPILE=""
136 default CC="$(CROSS_COMPILE)gcc -m32"
140 ## The Serial Console
143 # To Enable the Serial Console
144 default CONFIG_CONSOLE_SERIAL8250=1
146 ## Select the serial console baud rate
147 default TTYS0_BAUD=115200
148 #default TTYS0_BAUD=57600
149 #default TTYS0_BAUD=38400
150 #default TTYS0_BAUD=19200
151 #default TTYS0_BAUD=9600
152 #default TTYS0_BAUD=4800
153 #default TTYS0_BAUD=2400
154 #default TTYS0_BAUD=1200
156 # Select the serial console base port
157 default TTYS0_BASE=0x3f8
159 # Select the serial protocol
160 # This defaults to 8 data bits, 1 stop bit, and no parity
161 default TTYS0_LCS=0x3
164 ### Select the coreboot loglevel
166 ## EMERG 1 system is unusable
167 ## ALERT 2 action must be taken immediately
168 ## CRIT 3 critical conditions
169 ## ERR 4 error conditions
170 ## WARNING 5 warning conditions
171 ## NOTICE 6 normal but significant condition
172 ## INFO 7 informational
173 ## DEBUG 8 debug-level messages
174 ## SPEW 9 Way too many details
176 ## Request this level of debugging output
177 default DEFAULT_CONSOLE_LOGLEVEL=8
178 ## At a maximum only compile in this level of debugging
179 default MAXIMUM_CONSOLE_LOGLEVEL=8
186 default CONFIG_CBFS=0