1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
17 if CONFIG_GENERATE_PIRQ_TABLE
21 #compile cache_as_ram.c to auto.inc
22 makerule ./cache_as_ram_auto.inc
23 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
24 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
25 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
26 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
30 ## Build our 16 bit and 32 bit coreboot entry code
32 mainboardinit cpu/x86/16bit/entry16.inc
33 mainboardinit cpu/x86/32bit/entry32.inc
34 ldscript /cpu/x86/16bit/entry16.lds
35 ldscript /cpu/x86/32bit/entry32.lds
38 ## Build our reset vector (This is where coreboot is entered)
40 if CONFIG_USE_FALLBACK_IMAGE
41 mainboardinit cpu/x86/16bit/reset16.inc
42 ldscript /cpu/x86/16bit/reset16.lds
44 mainboardinit cpu/x86/32bit/reset32.inc
45 ldscript /cpu/x86/32bit/reset32.lds
48 ### Should this be in the northbridge code?
49 mainboardinit arch/i386/lib/cpu_reset.inc
52 ## Include an id string (For safe flashing)
54 mainboardinit arch/i386/lib/id.inc
55 ldscript /arch/i386/lib/id.lds
58 ### This is the early phase of coreboot startup
59 ### Things are delicate and we test to see if we should
60 ### failover to another image.
62 if CONFIG_USE_FALLBACK_IMAGE
63 ldscript /arch/i386/lib/failover.lds
64 # mainboardinit ./failover.inc
68 ### O.k. We aren't just an intermediary anymore!
74 mainboardinit cpu/x86/fpu_enable.inc
76 mainboardinit cpu/amd/model_lx/cache_as_ram.inc
77 mainboardinit ./cache_as_ram_auto.inc
80 ## Include the secondary Configuration files
85 chip northbridge/amd/lx
86 device pci_domain 0 on
89 chip southbridge/amd/cs5536
90 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
91 # SIRQ Mode = Active(Quiet) mode. Save power....
92 # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
93 # How to get these? Boot linux and do this:
95 register "lpc_serirq_enable" = "0x0000105a"
96 # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
97 register "lpc_serirq_polarity" = "0x0000EFA5"
98 # mode is high 10 bits (determined from code)
99 register "lpc_serirq_mode" = "1"
100 # Don't yet know how to find this.
101 register "enable_gpio_int_route" = "0x0D0C0700"
102 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
103 register "enable_USBP4_device" = "0" #0: host, 1:device
104 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
105 register "com1_enable" = "0"
106 register "com1_address" = "0x3F8"
107 register "com1_irq" = "4"
108 register "com2_enable" = "0"
109 register "com2_address" = "0x2F8"
110 register "com2_irq" = "3"
111 register "unwanted_vpci[0]" = "0" # End of list has a zero
112 device pci f.0 on # ISA Bridge
113 chip superio/winbond/w83627hf
114 device pnp 2e.0 off # Floppy
119 device pnp 2e.1 off # Parallel Port
123 device pnp 2e.2 on # Com1
127 device pnp 2e.3 on # Com2
131 device pnp 2e.5 on # Keyboard
137 device pnp 2e.6 off # CIR
140 device pnp 2e.7 off # GAME_MIDI_GIPO1
145 device pnp 2e.8 off end # GPIO2
146 device pnp 2e.9 off end # GPIO3
147 device pnp 2e.a off end # ACPI
148 device pnp 2e.b on # HW Monitor
154 device pci f.1 on end # Flash controller
155 device pci f.2 on end # IDE controller
156 device pci f.3 on end # Audio
157 device pci f.4 on end # OHCI
158 device pci f.5 on end # EHCI
162 # APIC cluster is late CPU init.
163 device apic_cluster 0 on
164 chip cpu/amd/model_lx