1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
5 #include <device/pci_ops.h>
6 #include <cpu/amd/sc520.h>
12 volatile unsigned char *irq;
17 int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
18 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
19 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
20 0xd30, 0xd31, 0xd32, 0xd33,
21 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
22 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
24 mmcr = (void *) 0xfffef000;
26 printk_err("mmcr is %p\n", mmcr);
27 for(i = 0; irqlist[i] >= 0; i++) {
28 irq = mmcr + irqlist[i];
29 printk_err("0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
34 /* TODO: finish up mmcr struct in sc520.h, and;
35 - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
37 static void enable_dev(struct device *dev) {
38 extern unsigned char *rom_start, *rom_end;
39 volatile struct mmcrpic *pic = MMCRPIC;
40 volatile struct mmcr *mmcr = MMCRDEFAULT;
42 /* msm586seg has this register set to a weird value.
43 * follow the board, not the manual!
46 /* currently, nothing in the device to use, so ignore it. */
47 printk_err("digital logic msm586 seg ENTER %s\n", __FUNCTION__);
50 /* from fuctory bios */
51 /* NOTE: the following interrupt settings made interrupts work
52 * for hard drive, and serial, but not for ethernet
54 /* just do what they say and nobody gets hurt. */
55 mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
56 /* all ints to level */
57 mmcr->pic.mpicmode = 0;
58 mmcr->pic.sl1picmode = 0;
59 mmcr->pic.sl2picmode = 0x80;
61 mmcr->pic.intpinpol = 0;
63 mmcr->pic.pit0map = 1;
64 mmcr->pic.uart1map = 0xc;
65 mmcr->pic.uart2map = 0xb;
67 mmcr->pic.ferrmap = 8;
68 mmcr->pic.gp0imap = 6;
69 mmcr->pic.gp1imap = 2;
70 mmcr->pic.gp2imap = 7;
71 mmcr->pic.gp6imap = 0x15;
72 mmcr->pic.gp7imap = 0x16;
73 mmcr->pic.gp10imap = 0x9;
74 mmcr->pic.gp9imap = 0x4;
81 printk_err("uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
83 printk_err("0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
84 printk_err("0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
86 /* The following block has NOT proven sufficient to get
87 * the VGA hardware to talk to us
89 /* let's set some mmcr stuff per the BIOS settings */
90 mmcr->dbctl.dbctl = 0x10;
92 mmcr->sysarb.menb = 0xf;
93 mmcr->sysarb.prictl = 0xc0000f0f;
94 /* this is bios setting, depends on sysarb above */
95 mmcr->hostbridge.ctl = 0x108;
96 printk_err("digital logic msm586 seg EXIT %s\n", __FUNCTION__);
99 mmcr->pio.data31_16 = 0xffbf;
102 mmcr->pic.pciintamap = 0xa;
104 /* END block where vga hardware still will not talk to us */
105 /* all we get from VGA I/O addresses are ffff etc.
107 mmcr->sysmap.adddecctl = 0x10;
109 /* VGA now talks to us, so this adddecctl was the trick.
110 * still no interrupts from enet.
111 * Let's try fixing the piodata stuff, as there may be
112 * some wire there not documented.
114 mmcr->pio.data31_16 = 0xffbf;
115 /* also, our sl?picmode needs to match fuctory bios */
116 mmcr->pic.sl1picmode = 0x80;
117 mmcr->pic.sl2picmode = 0x0;
118 /* and, finally, they do set gp5imap and we don't.
120 mmcr->pic.gp5imap = 0xd;
121 /* remaining problem: almost certainly, the irq table is bogus
122 * NO SHOCK as it came from fuctory bios.
123 * but let's try these 4 changes for now and see what shakes.
125 /* still not interrupts. */
126 /* their IRQ table is wrong. Just hardwire it */
128 char pciints[4] = {15, 15, 15, 15};
129 pci_assign_irqs(0, 12, pciints);
131 /* the assigned failed but we just noticed -- there is no
132 * dma mapping, and selftest on e100 requires that dma work
134 /* follow fuctory here */
135 mmcr->dmacontrol.extchanmapa = 0x3210;
137 /* hack for IDIOTIC need to fix rom_start */
138 printk_err("Patching rom_start due to sc520 limits\n");
139 rom_start = 0x2000000 + 0x40000;
140 rom_end = rom_start + PAYLOAD_SIZE - 1;
144 struct chip_operations mainboard_digitallogic_msm586seg_ops = {
145 CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")
146 .enable_dev = enable_dev