src/mainboard/digitallogic/adl855pc/romstage.c

   1 #define ASSEMBLY 1
   2
   3 #define ASM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #if 0
  10 #include <arch/smp/lapic.h>
  11 #endif
  12 #include <arch/hlt.h>
  13 //#include "option_table.h"
  14 #include <stdlib.h>
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "arch/i386/lib/console.c"
  18 #include "lib/ramtest.c"
  19 #include "southbridge/intel/i82801dx/i82801dx.h"
  20 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
  21 #include "northbridge/intel/i855/raminit.h"
  22
  23 #if 0
  24 #include "cpu/p6/apic_timer.c"
  25 #include "lib/delay.c"
  26 #endif
  27
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/intel/i855/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31 #include "cpu/x86/mtrr/earlymtrr.c"
  32 #include "cpu/x86/bist.h"
  33
  34 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  35
  36 static void hard_reset(void)
  37 {
  38         outb(0x0e, 0x0cf9);
  39 }
  40
  41 static void memreset_setup(void)
  42 {
  43 }
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47 }
  48
  49
  50
  51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  52 {
  53         /* nothing to do */
  54 }
  55
  56 static inline int spd_read_byte(unsigned device, unsigned address)
  57 {
  58         return smbus_read_byte(device, address);
  59 }
  60
  61 #include "northbridge/intel/i855/raminit.c"
  62 #include "northbridge/intel/i855/reset_test.c"
  63 #include "lib/generic_sdram.c"
  64
  65 static void main(unsigned long bist)
  66 {
  67         static const struct mem_controller memctrl[] = {
  68                 {
  69                         .d0 = PCI_DEV(0, 0, 1),
  70                         .channel0 = { (0xa<<3)|0, 0 },
  71                 },
  72         };
  73
  74         if (bist == 0) {
  75                 early_mtrr_init();
  76 #if 0
  77                 enable_lapic();
  78                 init_timer();
  79 #endif
  80         }
  81
  82         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  83         uart_init();
  84         console_init();
  85
  86
  87         /* Halt if there was a built in self test failure */
  88         report_bist_failure(bist);
  89
  90
  91 #if 0
  92         print_pci_devices();
  93 #endif
  94
  95         if(!bios_reset_detected()) {
  96                 enable_smbus();
  97 #if 0
  98         dump_spd_registers(&memctrl[0]);
  99         //              dump_smbus_registers();
 100 #endif
 101
 102
 103                 memreset_setup();
 104
 105                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 106
 107         }
 108 #if 0
 109         else {
 110                         /* clear memory 1meg */
 111         __asm__ volatile(
 112                 "1: \n\t"
 113                 "movl %0, %%fs:(%1)\n\t"
 114                 "addl $4,%1\n\t"
 115                 "subl $4,%2\n\t"
 116                 "jnz 1b\n\t"
 117                 :
 118                 : "a" (0), "D" (0), "c" (1024*1024)
 119                 );
 120
 121         }
 122 #endif
 123
 124 #if 0
 125         dump_pci_devices();
 126 #endif
 127 #if 0
 128         dump_pci_device(PCI_DEV(0, 0, 0));
 129 #endif
 130
 131 /*
 132 #if  0
 133         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 134 #else
 135 #if 0
 136         // Check 16MB of memory @ 0
 137         ram_check(0x00000000, 0x01000000);
 138 #else
 139         // Check 16MB of memory @ 2GB
 140         ram_check(0x80000000, 0x81000000);
 141 #endif
 142 #endif
 143 */
 144 }