src/mainboard/digitallogic/adl855pc/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3 #define ASM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #if 0
  10 #include <arch/smp/lapic.h>
  11 #endif
  12 #include <arch/hlt.h>
  13 //#include "option_table.h"
  14 #include <stdlib.h>
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "arch/i386/lib/console.c"
  18 #include "lib/ramtest.c"
  19 #include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
  20 #include "northbridge/intel/i855/raminit.h"
  21
  22 #if 0
  23 #include "cpu/p6/apic_timer.c"
  24 #include "lib/delay.c"
  25 #endif
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/intel/i855/debug.c"
  29 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  30 #include "cpu/x86/mtrr/earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 static void hard_reset(void)
  36 {
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void memreset_setup(void)
  41 {
  42 }
  43
  44 static void memreset(int controllers, const struct mem_controller *ctrl)
  45 {
  46 }
  47
  48
  49
  50 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  51 {
  52         /* nothing to do */
  53 }
  54
  55 static inline int spd_read_byte(unsigned device, unsigned address)
  56 {
  57         return smbus_read_byte(device, address);
  58 }
  59
  60 #include "northbridge/intel/i855/raminit.c"
  61 #include "northbridge/intel/i855/reset_test.c"
  62 #include "lib/generic_sdram.c"
  63
  64 static void main(unsigned long bist)
  65 {
  66         static const struct mem_controller memctrl[] = {
  67                 {
  68                         .d0 = PCI_DEV(0, 0, 1),
  69                         .channel0 = { (0xa<<3)|0, 0 },
  70                 },
  71         };
  72
  73         if (bist == 0) {
  74                 early_mtrr_init();
  75 #if 0
  76                 enable_lapic();
  77                 init_timer();
  78 #endif
  79         }
  80
  81         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  82         uart_init();
  83         console_init();
  84
  85
  86         /* Halt if there was a built in self test failure */
  87         report_bist_failure(bist);
  88
  89
  90 #if 0
  91         print_pci_devices();
  92 #endif
  93
  94         if(!bios_reset_detected()) {
  95                 enable_smbus();
  96 #if 0
  97         dump_spd_registers(&memctrl[0]);
  98         //              dump_smbus_registers();
  99 #endif
 100
 101
 102                 memreset_setup();
 103
 104                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 105
 106         }
 107 #if 0
 108         else {
 109                         /* clear memory 1meg */
 110         __asm__ volatile(
 111                 "1: \n\t"
 112                 "movl %0, %%fs:(%1)\n\t"
 113                 "addl $4,%1\n\t"
 114                 "subl $4,%2\n\t"
 115                 "jnz 1b\n\t"
 116                 :
 117                 : "a" (0), "D" (0), "c" (1024*1024)
 118                 );
 119
 120         }
 121 #endif
 122
 123 #if 0
 124         dump_pci_devices();
 125 #endif
 126 #if 0
 127         dump_pci_device(PCI_DEV(0, 0, 0));
 128 #endif
 129
 130 /*
 131 #if  0
 132         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 133 #else
 134 #if 0
 135         // Check 16MB of memory @ 0
 136         ram_check(0x00000000, 0x01000000);
 137 #else
 138         // Check 16MB of memory @ 2GB
 139         ram_check(0x80000000, 0x81000000);
 140 #endif
 141 #endif
 142 */
 143 }