src/mainboard/digitallogic/adl855pc/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/smp/lapic.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "ram/ramtest.c"
  13 #include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
  14 #include "northbridge/intel/i855pm/raminit.h"
  15
  16 #if 1
  17 #include "cpu/p6/apic_timer.c"
  18 #include "lib/delay.c"
  19 #endif
  20
  21 #include "cpu/p6/boot_cpu.c"
  22 #include "northbridge/intel/i855pm/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #include "cpu/p6/earlymtrr.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         outb(0x0e, 0x0cf9);
  32 }
  33
  34 static void memreset_setup(void)
  35 {
  36 }
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40 }
  41
  42
  43
  44 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  45 {
  46         /* nothing to do */
  47 }
  48
  49 static inline int spd_read_byte(unsigned device, unsigned address)
  50 {
  51         return smbus_read_byte(device, address);
  52 }
  53
  54 #include "northbridge/intel/i855pm/raminit.c"
  55 #include "northbridge/intel/i855pm/reset_test.c"
  56 #include "sdram/generic_sdram.c"
  57
  58 static void main(void)
  59 {
  60         static const struct mem_controller memctrl[] = {
  61                 {
  62                         .d0 = PCI_DEV(0, 0, 0),
  63                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  64                 },
  65         };
  66
  67 #if 1
  68         enable_lapic();
  69         init_timer();
  70 #endif
  71
  72         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
  73         uart_init();
  74         console_init();
  75
  76 #if 1
  77         print_pci_devices();
  78 #endif
  79         if(!bios_reset_detected()) {
  80                 enable_smbus();
  81 #if 1
  82 //              dump_spd_registers(&memctrl[0]);
  83                 dump_smbus_registers();
  84 #endif
  85
  86                 memreset_setup();
  87                 sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
  88         }
  89 #if 0
  90         else {
  91                         /* clear memory 1meg */
  92         __asm__ volatile(
  93                 "1: \n\t"
  94                 "movl %0, %%fs:(%1)\n\t"
  95                 "addl $4,%1\n\t"
  96                 "subl $4,%2\n\t"
  97                 "jnz 1b\n\t"
  98                 :
  99                 : "a" (0), "D" (0), "c" (1024*1024)
 100                 );
 101
 102         }
 103 #endif
 104
 105 #if 1
 106         dump_pci_devices();
 107 #endif
 108 #if 1
 109         dump_pci_device(PCI_DEV(0, 0, 0));
 110 #endif
 111
 112 /*
 113 #if  0
 114         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 115 #else
 116 #if 0
 117         // Check 16MB of memory @ 0
 118         ram_check(0x00000000, 0x01000000);
 119 #else
 120         // Check 16MB of memory @ 2GB
 121         ram_check(0x80000000, 0x81000000);
 122 #endif
 123 #endif
 124 */
 125 }