4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
9 #include <arch/smp/lapic.h>
12 //#include "option_table.h"
13 #include "pc80/mc146818rtc_early.c"
14 #include "pc80/serial.c"
15 #include "arch/i386/lib/console.c"
16 #include "ram/ramtest.c"
17 #include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
18 #include "northbridge/intel/i855pm/raminit.h"
21 #include "cpu/p6/apic_timer.c"
22 #include "lib/delay.c"
25 #include "cpu/x86/lapic/boot_cpu.c"
26 #include "northbridge/intel/i855pm/debug.c"
27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
28 #include "cpu/x86/mtrr/earlymtrr.c"
29 #include "cpu/x86/bist.h"
31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
34 static void hard_reset(void)
39 static void memreset_setup(void)
43 static void memreset(int controllers, const struct mem_controller *ctrl)
49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
54 static inline int spd_read_byte(unsigned device, unsigned address)
56 return smbus_read_byte(device, address);
59 #include "northbridge/intel/i855pm/raminit.c"
60 #include "northbridge/intel/i855pm/reset_test.c"
61 #include "sdram/generic_sdram.c"
63 static void main(unsigned long bist)
65 static const struct mem_controller memctrl[] = {
67 .d0 = PCI_DEV(0, 0, 1),
68 .channel0 = { (0xa<<3)|0, 0 },
80 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
84 /* Halt if there was a built in self test failure */
85 report_bist_failure(bist);
90 if(!bios_reset_detected()) {
93 dump_spd_registers(&memctrl[0]);
94 // dump_smbus_registers();
98 sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
102 /* clear memory 1meg */
105 "movl %0, %%fs:(%1)\n\t"
110 : "a" (0), "D" (0), "c" (1024*1024)
120 dump_pci_device(PCI_DEV(0, 0, 0));
125 ram_check(0x00000000, msr.lo+(msr.hi<<32));
128 // Check 16MB of memory @ 0
129 ram_check(0x00000000, 0x01000000);
131 // Check 16MB of memory @ 2GB
132 ram_check(0x80000000, 0x81000000);