3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_STREAM_START
27 ## ROM_SIZE is the size of boot ROM that this board will use.
28 default ROM_SIZE = 256*1024
35 ## Build code for the fallback boot
37 default HAVE_FALLBACK_BOOT=1
42 default HAVE_MP_TABLE=0
45 ## Build code to reset the motherboard from linuxBIOS
47 default HAVE_HARD_RESET=1
50 ## Build code to export a programmable irq routing table
52 default HAVE_PIRQ_TABLE=1
53 default IRQ_SLOT_COUNT=5
57 ## Build code to export a CMOS option table
59 default HAVE_OPTION_TABLE=1
62 ### LinuxBIOS layout values
65 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
66 default ROM_IMAGE_SIZE = 65536
69 ## Use a small 8K stack
71 default STACK_SIZE=0x2000
74 ## Use a small 16K heap
76 default HEAP_SIZE=0x4000
79 ## Only use the option table in a normal image
81 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
82 default USE_OPTION_TABLE = 0
85 ## Compute the location and size of where this firmware image
86 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
89 default ROM_SECTION_SIZE = FALLBACK_SIZE
90 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
92 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
93 default ROM_SECTION_OFFSET = 0
97 ## Compute the start location and size size of
98 ## The linuxBIOS bootloader.
100 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
101 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
102 default CONFIG_ROM_STREAM = 1
105 ## Compute where this copy of linuxBIOS will start in the boot rom
107 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
110 ## Compute a range of ROM that can cached to speed up linuxBIOS,
113 ## XIP_ROM_SIZE must be a power of 2.
114 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
116 default XIP_ROM_SIZE=65536
117 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
120 ## Set all of the defaults for an x86 architecture
126 ## Build the objects we have code for in this directory.
136 makerule ./failover.E
137 depends "$(MAINBOARD)/failover.c"
138 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
141 makerule ./failover.inc
142 depends "./failover.E ./romcc"
143 action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
147 depends "$(MAINBOARD)/auto.c"
148 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
151 depends "./auto.E ./romcc"
152 action "./romcc -O -mcpu=c3 ./auto.E "
156 ## Build our 16 bit and 32 bit linuxBIOS entry code
158 mainboardinit cpu/i386/entry16.inc
159 mainboardinit cpu/i386/entry32.inc
160 ldscript /cpu/i386/entry16.lds
161 ldscript /cpu/i386/entry32.lds
164 ## Build our reset vector (This is where linuxBIOS is entered)
166 if USE_FALLBACK_IMAGE
167 mainboardinit cpu/i386/reset16.inc
168 ldscript /cpu/i386/reset16.lds
170 mainboardinit cpu/i386/reset32.inc
171 ldscript /cpu/i386/reset32.lds
174 ### Should this be in the northbridge code?
175 mainboardinit arch/i386/lib/cpu_reset.inc
178 ## Include an id string (For safe flashing)
180 mainboardinit arch/i386/lib/id.inc
181 ldscript /arch/i386/lib/id.lds
186 # mainboardinit cpu/p6/earlymtrr.inc
189 ### This is the early phase of linuxBIOS startup
190 ### Things are delicate and we test to see if we should
191 ### failover to another image.
193 if USE_FALLBACK_IMAGE
194 ldscript /arch/i386/lib/failover.lds
195 mainboardinit ./failover.inc
199 ### O.k. We aren't just an intermediary anymore!
205 mainboardinit ./auto.inc
208 ## Include the secondary Configuration files
213 northbridge intel/i855pm "i855pm"
216 southbridge intel/i82801dbm "i82801dbm"
225 register "enable_usb" = "0"
226 register "enable_native_ide" = "0"
235 ## Include the old serial code for those few places that still need it.
237 mainboardinit pc80/serial.inc
238 mainboardinit arch/i386/lib/console.inc