src/mainboard/digitallogic/adl855pc/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  17 #object reset.o
  18
  19 ##
  20 ## Romcc output
  21 ##
  22 makerule ./failover.E
  23         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  24         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  25 end
  26
  27 makerule ./failover.inc
  28         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  29         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  30 end
  31
  32 makerule ./auto.E
  33         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  34         action  "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  35 end
  36 makerule ./auto.inc
  37         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  38         action  "../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  39 end
  40
  41 ##
  42 ## Build our 16 bit and 32 bit coreboot entry code
  43 ##
  44 mainboardinit cpu/x86/16bit/entry16.inc
  45 mainboardinit cpu/x86/32bit/entry32.inc
  46 ldscript /cpu/x86/16bit/entry16.lds
  47 ldscript /cpu/x86/32bit/entry32.lds
  48
  49 ##
  50 ## Build our reset vector (This is where coreboot is entered)
  51 ##
  52 if CONFIG_USE_FALLBACK_IMAGE
  53         mainboardinit cpu/x86/16bit/reset16.inc
  54         ldscript /cpu/x86/16bit/reset16.lds
  55 else
  56         mainboardinit cpu/x86/32bit/reset32.inc
  57         ldscript /cpu/x86/32bit/reset32.lds
  58 end
  59
  60 ### Should this be in the northbridge code?
  61 mainboardinit arch/i386/lib/cpu_reset.inc
  62
  63 ##
  64 ## Include an id string (For safe flashing)
  65 ##
  66 mainboardinit arch/i386/lib/id.inc
  67 ldscript /arch/i386/lib/id.lds
  68
  69 ###
  70 ### This is the early phase of coreboot startup
  71 ### Things are delicate and we test to see if we should
  72 ### failover to another image.
  73 ###
  74 if CONFIG_USE_FALLBACK_IMAGE
  75         ldscript /arch/i386/lib/failover.lds
  76         mainboardinit ./failover.inc
  77 end
  78
  79 ###
  80 ### O.k. We aren't just an intermediary anymore!
  81 ###
  82
  83 ##
  84 ## Setup RAM
  85 ##
  86 mainboardinit cpu/x86/fpu/enable_fpu.inc
  87 mainboardinit cpu/x86/mmx/enable_mmx.inc
  88 mainboardinit cpu/x86/sse/enable_sse.inc
  89 mainboardinit ./auto.inc
  90 mainboardinit cpu/x86/sse/disable_sse.inc
  91 mainboardinit cpu/x86/mmx/disable_mmx.inc
  92
  93 ##
  94 ## Include the secondary Configuration files
  95 ##
  96 dir /pc80
  97 config chip.h
  98
  99 ## This does not look right but it is a literal conversion of the
 100 ## old version of this file.
 101 chip northbridge/intel/i855pm
 102         device pci_domain 0 on
 103                 device pci 0.0 on end
 104                 device pci 1.0 on end
 105                 chip southbridge/intel/i82801dbm
 106 #                       pci 11.0 on end
 107 #                       pci 11.1 on end
 108 #                       pci 11.2 on end
 109 #                       pci 11.3 on end
 110 #                       pci 11.4 on end
 111 #                       pci 11.5 on end
 112 #                       pci 11.6 on end
 113 #                       pci 12.0 on end
 114                         register "enable_usb" = "0"
 115                         register "enable_native_ide" = "0"
 116                         register "enable_usb" = "0"
 117                         register "enable_native_ide" = "0"
 118                         chip superio/winbond/w83627hf # link 1
 119                                 device pnp 2e.0 on      #  Floppy
 120                                          io 0x60 = 0x3f0
 121                                         irq 0x70 = 6
 122                                         drq 0x74 = 2
 123                                 end
 124                                 device pnp 2e.1 off     #  Parallel Port
 125                                          io 0x60 = 0x378
 126                                         irq 0x70 = 7
 127                                 end
 128                                 device pnp 2e.2 on      #  Com1
 129                                          io 0x60 = 0x3f8
 130                                         irq 0x70 = 4
 131                                 end
 132                                 device pnp 2e.3 off     #  Com2
 133                                         io 0x60 = 0x2f8
 134                                         irq 0x70 = 3
 135                                 end
 136                                 device pnp 2e.5 on      #  Keyboard
 137                                          io 0x60 = 0x60
 138                                          io 0x62 = 0x64
 139                                         irq 0x70 = 1
 140                                         irq 0x72 = 12
 141                                 end
 142                                 device pnp 2e.6 off end #  CIR
 143                                 device pnp 2e.7 off end #  GAME_MIDI_GIPO1
 144                                 device pnp 2e.8 off end #  GPIO2
 145                                 device pnp 2e.9 off end #  GPIO3
 146                                 device pnp 2e.a off end #  ACPI
 147                                 device pnp 2e.b on      #  HW Monitor
 148                                          io 0x60 = 0x290
 149                                 end
 150                                 register "com1" = "{1}"
 151                         #       register "com1" = "{1, 0, 0x3f8, 4}"
 152                         #       register "lpt" = "{1}"
 153                         end
 154                 end
 155         end
 156         device apic_cluster 0 on
 157                 chip cpu/intel/socket_mPGA479M
 158                         device apic 0 on end
 159                 end
 160         end
 161 end