2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_PIRQ_TABLE object irq_tables.o end
53 depends "$(MAINBOARD)/failover.c ./romcc"
54 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
57 makerule ./failover.inc
58 depends "$(MAINBOARD)/failover.c ./romcc"
59 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
63 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
64 action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
67 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
68 action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
72 ## Build our 16 bit and 32 bit linuxBIOS entry code
74 mainboardinit cpu/x86/16bit/entry16.inc
75 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/16bit/entry16.lds
77 ldscript /cpu/x86/32bit/entry32.lds
80 ## Build our reset vector (This is where linuxBIOS is entered)
83 mainboardinit cpu/x86/16bit/reset16.inc
84 ldscript /cpu/x86/16bit/reset16.lds
86 mainboardinit cpu/x86/32bit/reset32.inc
87 ldscript /cpu/x86/32bit/reset32.lds
90 ### Should this be in the northbridge code?
91 mainboardinit arch/i386/lib/cpu_reset.inc
94 ## Include an id string (For safe flashing)
96 mainboardinit arch/i386/lib/id.inc
97 ldscript /arch/i386/lib/id.lds
100 ### This is the early phase of linuxBIOS startup
101 ### Things are delicate and we test to see if we should
102 ### failover to another image.
104 if USE_FALLBACK_IMAGE
105 ldscript /arch/i386/lib/failover.lds
106 mainboardinit ./failover.inc
110 ### O.k. We aren't just an intermediary anymore!
116 mainboardinit cpu/x86/fpu/enable_fpu.inc
117 mainboardinit cpu/x86/mmx/enable_mmx.inc
118 mainboardinit cpu/x86/sse/enable_sse.inc
119 mainboardinit ./auto.inc
120 mainboardinit cpu/x86/sse/disable_sse.inc
121 mainboardinit cpu/x86/mmx/disable_mmx.inc
124 ## Include the secondary Configuration files
129 ## This does not look right but it is a literal conversion of the
130 ## old version of this file.
131 chip northbridge/intel/i855pm
132 device pci_domain 0 on
133 device pci 0.0 on end
134 device pci 1.0 on end
135 chip southbridge/intel/i82801dbm
144 register "enable_usb" = "0"
145 register "enable_native_ide" = "0"
146 register "enable_usb" = "0"
147 register "enable_native_ide" = "0"
148 chip superio/winbond/w83627hf # link 1
149 device pnp 2e.0 on # Floppy
154 device pnp 2e.1 off # Parallel Port
158 device pnp 2e.2 on # Com1
162 device pnp 2e.3 off # Com2
166 device pnp 2e.5 on # Keyboard
172 device pnp 2e.6 off end # CIR
173 device pnp 2e.7 off end # GAME_MIDI_GIPO1
174 device pnp 2e.8 off end # GPIO2
175 device pnp 2e.9 off end # GPIO3
176 device pnp 2e.a off end # ACPI
177 device pnp 2e.b on # HW Monitor
180 register "com1" = "{1}"
181 # register "com1" = "{1, 0, 0x3f8, 4}"
182 # register "lpt" = "{1}"
186 device apic_cluster 0 on
187 chip cpu/intel/socket_mPGA479M