2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
6 #include <cpu/x86/lapic.h>
8 #include <console/console.h>
9 #include "lib/ramtest.c"
10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
11 #include "northbridge/intel/e7520/raminit.h"
12 #include "superio/nsc/pc8374/pc8374_early_init.c"
13 #include "cpu/x86/lapic/boot_cpu.c"
14 #include "cpu/x86/mtrr/earlymtrr.c"
17 // Remove comment if resets in this file are actually used.
19 #include "s1850_fixups.c"
20 #include "northbridge/intel/e7520/memory_initialized.c"
21 #include "cpu/x86/bist.h"
24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
26 #define DEVPRES_CONFIG ( \
34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
36 static inline int spd_read_byte(unsigned device, unsigned address)
38 return smbus_read_byte(device, address);
41 #include "northbridge/intel/e7520/raminit.c"
42 #include "lib/generic_sdram.c"
44 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
47 #define nftransport 0xc
52 #define ipmidata 0xca0
55 static inline void ibfzero(void)
57 while(inb(ipmicsr) & (1<<IBF))
60 static inline void clearobf(void)
65 static inline void waitobf(void)
67 while((inb(ipmicsr) & (1<<OBF)) == 0)
70 /* quite possibly the stupidest interface ever designed. */
71 static inline void first_cmd_byte(unsigned char byte)
81 static inline void next_cmd_byte(unsigned char byte)
89 static inline void last_cmd_byte(unsigned char byte)
98 static inline void read_response_byte(void)
101 if ((inb(ipmicsr)>>6) != 1)
107 outb(0x68, ipmidata);
109 /* see if it is done */
110 if ((inb(ipmicsr)>>6) != 1){
111 /* wait for the dummy read. Which describes this protocol */
117 static inline void ipmidelay(void)
120 for(i = 0; i < 1000; i++) {
125 static inline void bmc_foad(void)
128 /* be safe; make sure it is really ready */
129 while ((inb(ipmicsr)>>6)) {
133 first_cmd_byte(nftransport << 2);
143 /* end IPMI garbage */
145 #include "arch/i386/lib/stages.c"
147 static void main(unsigned long bist)
154 static const struct mem_controller mch[] = {
158 .f0 = PCI_DEV(0, 0x00, 0),
159 .f1 = PCI_DEV(0, 0x00, 1),
160 .f2 = PCI_DEV(0, 0x00, 2),
161 .f3 = PCI_DEV(0, 0x00, 3),
163 /* the wiring on this part is really messed up */
164 /* this is my best guess so far */
165 .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
166 .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
171 /* observed from serialice */
172 static const u8 earlyinit[] = {
181 /* using SerialICE, we've seen this basic reset sequence on the dell.
182 * we don't understand it as it uses undocumented registers, but
183 * we're going to clone it.
185 /* enable a hidden device. */
186 b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
188 pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
190 /* read-write lock in CMOS on LPC bridge on ICH5 */
191 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
193 /* operate on undocumented device */
194 l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
196 pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
198 l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
200 pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
202 /* disable undocumented device */
203 b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
205 pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
207 /* set up LPC bridge bits, some of which reply on undocumented
211 b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
213 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
215 b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
217 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
219 /* ACPI base address */
220 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
222 /* Enable specific ACPI features */
223 b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
225 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
229 outw(w|0x800, 0x868);
235 dell does this so leave it here so I don't forget
238 pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
245 /* another device enable? */
246 b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
248 pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
251 l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
252 do_reset = l & 0x8000000;
254 pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
261 /* Skip this if there was a built in self test failure */
263 if (memory_initialized()) {
267 /* Setup the console */
268 mainboard_set_ich5();
270 pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
274 /* stuff we seem to need */
275 pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
278 pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
280 /* keep this in mind.
281 SerialICE-hlp: outb 002e <= 23
282 SerialICE-hlp: inb 002f => 05
283 SerialICE-hlp: outb 002f <= 05
284 SerialICE-hlp: outb 002e <= 24
285 SerialICE-hlp: inb 002f => c1
286 SerialICE-hlp: outb 002f <= c1
289 /* Halt if there was a built in self test failure */
290 // report_bist_failure(bist);
292 /* MOVE ME TO A BETTER LOCATION !!! */
293 /* config LPC decode for flash memory access */
295 dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
296 if (dev == PCI_DEV_INVALID) {
297 die("Missing ich5?");
299 pci_write_config32(dev, 0xe8, 0x00000000);
300 pci_write_config8(dev, 0xf0, 0x00);
303 display_cpuid_update_microcode();
312 // dump_spd_registers(&cpu[0]);
314 for(i = 0; i < 1; i++) {
315 dump_spd_registers();
322 // dump_ipmi_registers();
323 mainboard_set_e7520_leds();
325 sdram_initialize(ARRAY_SIZE(mch), mch);
330 dump_pci_device(PCI_DEV(0, 0x00, 0));
331 // dump_bar14(PCI_DEV(0, 0x00, 0));
334 #if 1 // temporarily disabled
335 /* Check the first 1M */
336 // ram_check(0x00000000, 0x000100000);
337 // ram_check(0x00000000, 0x000a0000);
338 // ram_check(0x00100000, 0x01000000);
339 ram_check(0x00100000, 0x00100100);
340 /* check the first 1M in the 3rd Gig */
341 // ram_check(0x30100000, 0x31000000);
344 ram_check(0x00000000, 0x02000000);