src/mainboard/dell/s1850/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc8374/pc8374_early_init.c"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 // Remove comment if resets in this file are actually used.
  18 // #include "reset.c"
  19 #include "s1850_fixups.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22
  23 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  24
  25 #define DEVPRES_CONFIG  ( \
  26         DEVPRES_D0F0 | \
  27         DEVPRES_D1F0 | \
  28         DEVPRES_D2F0 | \
  29         DEVPRES_D3F0 | \
  30         DEVPRES_D4F0 | \
  31         DEVPRES_D6F0 | \
  32         0 )
  33 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  34
  35 static inline int spd_read_byte(unsigned device, unsigned address)
  36 {
  37         return smbus_read_byte(device, address);
  38 }
  39
  40 #include "northbridge/intel/e7520/raminit.c"
  41 #include "lib/generic_sdram.c"
  42
  43 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  44  */
  45
  46 #define nftransport  0xc
  47
  48 #define OBF  0
  49 #define IBF 1
  50
  51 #define ipmidata  0xca0
  52 #define ipmicsr  0xca4
  53
  54 static inline void  ibfzero(void)
  55 {
  56         while(inb(ipmicsr) &  (1<<IBF))
  57                 ;
  58 }
  59 static inline void  clearobf(void)
  60 {
  61         (void) inb(ipmidata);
  62 }
  63
  64 static inline void  waitobf(void)
  65 {
  66         while((inb(ipmicsr) &  (1<<OBF)) == 0)
  67                 ;
  68 }
  69 /* quite possibly the stupidest interface ever designed. */
  70 static inline void  first_cmd_byte(unsigned char byte)
  71 {
  72         ibfzero();
  73         clearobf();
  74         outb(0x61, ipmicsr);
  75         ibfzero();
  76         clearobf();
  77         outb(byte, ipmidata);
  78 }
  79
  80 static inline void  next_cmd_byte(unsigned char byte)
  81 {
  82
  83         ibfzero();
  84         clearobf();
  85         outb(byte, ipmidata);
  86 }
  87
  88 static inline void  last_cmd_byte(unsigned char byte)
  89 {
  90         outb(0x62, ipmicsr);
  91
  92         ibfzero();
  93         clearobf();
  94         outb(byte,  ipmidata);
  95 }
  96
  97 static inline void read_response_byte(void)
  98 {
  99         int val = -1;
 100         if ((inb(ipmicsr)>>6) != 1)
 101                 return;
 102
 103         ibfzero();
 104         waitobf();
 105         val = inb(ipmidata);
 106         outb(0x68, ipmidata);
 107
 108         /* see if it is done */
 109         if ((inb(ipmicsr)>>6) != 1){
 110                 /* wait for the dummy read. Which describes this protocol */
 111                 waitobf();
 112                 (void)inb(ipmidata);
 113         }
 114 }
 115
 116 static inline void ipmidelay(void)
 117 {
 118         int i;
 119         for(i = 0; i < 1000; i++) {
 120                 inb(0x80);
 121         }
 122 }
 123
 124 static inline void bmc_foad(void)
 125 {
 126         unsigned char c;
 127         /* be safe; make sure it is really ready */
 128         while ((inb(ipmicsr)>>6)) {
 129                 outb(0x60, ipmicsr);
 130                 inb(ipmidata);
 131         }
 132         first_cmd_byte(nftransport << 2);
 133         ipmidelay();
 134         next_cmd_byte(0x12);
 135         ipmidelay();
 136         next_cmd_byte(2);
 137         ipmidelay();
 138         last_cmd_byte(3);
 139         ipmidelay();
 140 }
 141
 142 /* end IPMI garbage */
 143
 144 #include "arch/i386/lib/stages.c"
 145
 146 static void main(unsigned long bist)
 147 {
 148         u8 b;
 149         u16 w;
 150         u32 l;
 151         int do_reset;
 152         /*
 153          *
 154          *
 155          */
 156         static const struct mem_controller mch[] = {
 157                 {
 158                         .node_id = 0,
 159                         /*
 160                         .f0 = PCI_DEV(0, 0x00, 0),
 161                         .f1 = PCI_DEV(0, 0x00, 1),
 162                         .f2 = PCI_DEV(0, 0x00, 2),
 163                         .f3 = PCI_DEV(0, 0x00, 3),
 164                         */
 165                         /* the wiring on this part is really messed up */
 166                         /* this is my best guess so far */
 167                         .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
 168                         .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
 169                 }
 170         };
 171
 172         /* superio setup */
 173         /* observed from serialice */
 174         static const u8 earlyinit[] = {
 175                 0x21, 0x11, 0x11,
 176                 0x22, 1, 1,
 177                 0x23, 05, 05,
 178                 0x24, 0x81, 0x81,
 179                 0x26, 0, 0,
 180                 0,
 181         };
 182
 183         /* using SerialICE, we've seen this basic reset sequence on the dell.
 184          * we don't understand it as it uses undocumented registers, but
 185          * we're going to clone it.
 186          */
 187         /* enable a hidden device. */
 188         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 189         b |= 0x8;
 190         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 191
 192         /* read-write lock in CMOS on LPC bridge on ICH5 */
 193         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 194
 195         /* operate on undocumented device */
 196         l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
 197         l |= 0x1000;
 198         pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
 199
 200         l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
 201         l |= 0x8000;
 202         pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
 203
 204         /* disable undocumented device */
 205         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 206         b &= ~0x8;
 207         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 208
 209         /* set up LPC bridge bits, some of which reply on undocumented
 210          * registers
 211          */
 212
 213         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
 214         b |= 4;
 215         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
 216
 217         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
 218         b |= 2;
 219         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
 220
 221         /* ACPI base address */
 222         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 223
 224         /* Enable specific ACPI features */
 225         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
 226         b |= 0x10;
 227         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
 228
 229         /* ACPI control */
 230         w = inw(0x868);
 231         outw(w|0x800, 0x868);
 232         w = inw(0x866);
 233         outw(w|2, 0x866);
 234
 235 #if 0
 236         /*seriaice shows
 237         dell does this so leave it here so I don't forget
 238          */
 239         /* SMBUS */
 240         pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
 241
 242         /* unknown */
 243         b = inb(0x8c2);
 244         outb(0xdf, 0x8c2);
 245 #endif
 246
 247         /* another device enable? */
 248         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 249         b |= 2;
 250         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 251
 252         /* ?? */
 253         l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
 254         do_reset = l & 0x8000000;
 255         l |= 0x8000000;
 256         pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
 257
 258         if (! do_reset) {
 259                 outb(2, 0xcf9);
 260                 outb(6, 0xcf9);
 261         }
 262         if (bist == 0) {
 263                 /* Skip this if there was a built in self test failure */
 264                 early_mtrr_init();
 265                 if (memory_initialized()) {
 266                         skip_romstage();
 267                 }
 268         }
 269         /* Setup the console */
 270         mainboard_set_ich5();
 271         //bmc_foad();
 272         pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 273         uart_init();
 274         console_init();
 275
 276         /* stuff we seem to need */
 277         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 278
 279         /* GPIOs */
 280         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
 281
 282         /* keep this in mind.
 283         SerialICE-hlp: outb 002e <= 23
 284         SerialICE-hlp:  inb 002f => 05
 285         SerialICE-hlp: outb 002f <= 05
 286         SerialICE-hlp: outb 002e <= 24
 287         SerialICE-hlp:  inb 002f => c1
 288         SerialICE-hlp: outb 002f <= c1
 289          */
 290
 291         /* Halt if there was a built in self test failure */
 292 //      report_bist_failure(bist);
 293
 294         /* MOVE ME TO A BETTER LOCATION !!! */
 295         /* config LPC decode for flash memory access */
 296         device_t dev;
 297         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 298         if (dev == PCI_DEV_INVALID) {
 299                 die("Missing ich5?");
 300         }
 301         pci_write_config32(dev, 0xe8, 0x00000000);
 302         pci_write_config8(dev, 0xf0, 0x00);
 303
 304 #if 0
 305         display_cpuid_update_microcode();
 306 #endif
 307 #if 1
 308         print_pci_devices();
 309 #endif
 310 #if 1
 311         enable_smbus();
 312 #endif
 313 #if 0
 314 //      dump_spd_registers(&cpu[0]);
 315         int i;
 316         for(i = 0; i < 1; i++) {
 317                 dump_spd_registers();
 318         }
 319 #endif
 320 #if 1
 321         show_dram_slots();
 322 #endif
 323         disable_watchdogs();
 324 //      dump_ipmi_registers();
 325         mainboard_set_e7520_leds();
 326
 327         sdram_initialize(ARRAY_SIZE(mch), mch);
 328 #if 0
 329         dump_pci_devices();
 330 #endif
 331 #if 1
 332         dump_pci_device(PCI_DEV(0, 0x00, 0));
 333 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 334 #endif
 335
 336 #if 1 // temporarily disabled
 337         /* Check the first 1M */
 338 //      ram_check(0x00000000, 0x000100000);
 339 //      ram_check(0x00000000, 0x000a0000);
 340 //      ram_check(0x00100000, 0x01000000);
 341         ram_check(0x00100000, 0x00100100);
 342         /* check the first 1M in the 3rd Gig */
 343 //      ram_check(0x30100000, 0x31000000);
 344 #endif
 345 #if 0
 346         ram_check(0x00000000, 0x02000000);
 347 #endif
 348
 349 #if 0
 350         while(1) {
 351                 hlt();
 352         }
 353 #endif
 354 }
 355