src/mainboard/dell/s1850/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc8374/pc8374_early_init.c"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 // Remove comment if resets in this file are actually used.
  18 // #include "reset.c"
  19 #include "s1850_fixups.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22
  23 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  24
  25 #define DEVPRES_CONFIG  ( \
  26         DEVPRES_D0F0 | \
  27         DEVPRES_D1F0 | \
  28         DEVPRES_D2F0 | \
  29         DEVPRES_D3F0 | \
  30         DEVPRES_D4F0 | \
  31         DEVPRES_D6F0 | \
  32         0 )
  33 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  34
  35 static inline int spd_read_byte(unsigned device, unsigned address)
  36 {
  37         return smbus_read_byte(device, address);
  38 }
  39
  40 /* this is very highly mainboard dependent, related to wiring */
  41 /* from factory BIOS via lspci */
  42 #define DIMM_MAP_LOGICAL 0x2841
  43 #include "northbridge/intel/e7520/raminit.c"
  44 #include "lib/generic_sdram.c"
  45
  46 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  47  */
  48
  49 #define nftransport  0xc
  50
  51 #define OBF  0
  52 #define IBF 1
  53
  54 #define ipmidata  0xca0
  55 #define ipmicsr  0xca4
  56
  57 static inline void  ibfzero(void)
  58 {
  59         while(inb(ipmicsr) &  (1<<IBF))
  60                 ;
  61 }
  62 static inline void  clearobf(void)
  63 {
  64         (void) inb(ipmidata);
  65 }
  66
  67 static inline void  waitobf(void)
  68 {
  69         while((inb(ipmicsr) &  (1<<OBF)) == 0)
  70                 ;
  71 }
  72 /* quite possibly the stupidest interface ever designed. */
  73 static inline void  first_cmd_byte(unsigned char byte)
  74 {
  75         ibfzero();
  76         clearobf();
  77         outb(0x61, ipmicsr);
  78         ibfzero();
  79         clearobf();
  80         outb(byte, ipmidata);
  81 }
  82
  83 static inline void  next_cmd_byte(unsigned char byte)
  84 {
  85
  86         ibfzero();
  87         clearobf();
  88         outb(byte, ipmidata);
  89 }
  90
  91 static inline void  last_cmd_byte(unsigned char byte)
  92 {
  93         outb(0x62, ipmicsr);
  94
  95         ibfzero();
  96         clearobf();
  97         outb(byte,  ipmidata);
  98 }
  99
 100 static inline void read_response_byte(void)
 101 {
 102         int val = -1;
 103         if ((inb(ipmicsr)>>6) != 1)
 104                 return;
 105
 106         ibfzero();
 107         waitobf();
 108         val = inb(ipmidata);
 109         outb(0x68, ipmidata);
 110
 111         /* see if it is done */
 112         if ((inb(ipmicsr)>>6) != 1){
 113                 /* wait for the dummy read. Which describes this protocol */
 114                 waitobf();
 115                 (void)inb(ipmidata);
 116         }
 117 }
 118
 119 static inline void ipmidelay(void)
 120 {
 121         int i;
 122         for(i = 0; i < 1000; i++) {
 123                 inb(0x80);
 124         }
 125 }
 126
 127 static inline void bmc_foad(void)
 128 {
 129         unsigned char c;
 130         /* be safe; make sure it is really ready */
 131         while ((inb(ipmicsr)>>6)) {
 132                 outb(0x60, ipmicsr);
 133                 inb(ipmidata);
 134         }
 135         first_cmd_byte(nftransport << 2);
 136         ipmidelay();
 137         next_cmd_byte(0x12);
 138         ipmidelay();
 139         next_cmd_byte(2);
 140         ipmidelay();
 141         last_cmd_byte(3);
 142         ipmidelay();
 143 }
 144
 145 /* end IPMI garbage */
 146
 147 #include "arch/i386/lib/stages.c"
 148
 149 static void main(unsigned long bist)
 150 {
 151         u8 b;
 152         u16 w;
 153         u32 l;
 154         int do_reset;
 155         /*
 156          *
 157          *
 158          */
 159         static const struct mem_controller mch[] = {
 160                 {
 161                         .node_id = 0,
 162                         /*
 163                         .f0 = PCI_DEV(0, 0x00, 0),
 164                         .f1 = PCI_DEV(0, 0x00, 1),
 165                         .f2 = PCI_DEV(0, 0x00, 2),
 166                         .f3 = PCI_DEV(0, 0x00, 3),
 167                         */
 168                         /* the wiring on this part is really messed up */
 169                         /* this is my best guess so far */
 170                         .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
 171                         .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
 172                 }
 173         };
 174
 175         /* superio setup */
 176         /* observed from serialice */
 177         static const u8 earlyinit[] = {
 178                 0x21, 0x11, 0x11,
 179                 0x22, 1, 1,
 180                 0x23, 05, 05,
 181                 0x24, 0x81, 0x81,
 182                 0x26, 0, 0,
 183                 0,
 184         };
 185
 186         /* using SerialICE, we've seen this basic reset sequence on the dell.
 187          * we don't understand it as it uses undocumented registers, but
 188          * we're going to clone it.
 189          */
 190         /* enable a hidden device. */
 191         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 192         b |= 0x8;
 193         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 194
 195         /* read-write lock in CMOS on LPC bridge on ICH5 */
 196         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 197
 198         /* operate on undocumented device */
 199         l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
 200         l |= 0x1000;
 201         pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
 202
 203         l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
 204         l |= 0x8000;
 205         pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
 206
 207         /* disable undocumented device */
 208         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 209         b &= ~0x8;
 210         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 211
 212         /* set up LPC bridge bits, some of which reply on undocumented
 213          * registers
 214          */
 215
 216         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
 217         b |= 4;
 218         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
 219
 220         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
 221         b |= 2;
 222         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
 223
 224         /* ACPI base address */
 225         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 226
 227         /* Enable specific ACPI features */
 228         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
 229         b |= 0x10;
 230         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
 231
 232         /* ACPI control */
 233         w = inw(0x868);
 234         outw(w|0x800, 0x868);
 235         w = inw(0x866);
 236         outw(w|2, 0x866);
 237
 238 #if 0
 239         /*seriaice shows
 240         dell does this so leave it here so I don't forget
 241          */
 242         /* SMBUS */
 243         pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
 244
 245         /* unknown */
 246         b = inb(0x8c2);
 247         outb(0xdf, 0x8c2);
 248 #endif
 249
 250         /* another device enable? */
 251         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 252         b |= 2;
 253         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 254
 255         /* ?? */
 256         l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
 257         do_reset = l & 0x8000000;
 258         l |= 0x8000000;
 259         pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
 260
 261         if (! do_reset) {
 262                 outb(2, 0xcf9);
 263                 outb(6, 0xcf9);
 264         }
 265         if (bist == 0) {
 266                 /* Skip this if there was a built in self test failure */
 267                 early_mtrr_init();
 268                 if (memory_initialized()) {
 269                         skip_romstage();
 270                 }
 271         }
 272         /* Setup the console */
 273         mainboard_set_ich5();
 274         //bmc_foad();
 275         pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 276         uart_init();
 277         console_init();
 278
 279         /* stuff we seem to need */
 280         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 281
 282         /* GPIOs */
 283         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
 284
 285         /* keep this in mind.
 286         SerialICE-hlp: outb 002e <= 23
 287         SerialICE-hlp:  inb 002f => 05
 288         SerialICE-hlp: outb 002f <= 05
 289         SerialICE-hlp: outb 002e <= 24
 290         SerialICE-hlp:  inb 002f => c1
 291         SerialICE-hlp: outb 002f <= c1
 292          */
 293
 294         /* Halt if there was a built in self test failure */
 295 //      report_bist_failure(bist);
 296
 297         /* MOVE ME TO A BETTER LOCATION !!! */
 298         /* config LPC decode for flash memory access */
 299         device_t dev;
 300         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 301         if (dev == PCI_DEV_INVALID) {
 302                 die("Missing ich5?");
 303         }
 304         pci_write_config32(dev, 0xe8, 0x00000000);
 305         pci_write_config8(dev, 0xf0, 0x00);
 306
 307 #if 0
 308         display_cpuid_update_microcode();
 309 #endif
 310 #if 1
 311         print_pci_devices();
 312 #endif
 313 #if 1
 314         enable_smbus();
 315 #endif
 316 #if 0
 317 //      dump_spd_registers(&cpu[0]);
 318         int i;
 319         for(i = 0; i < 1; i++) {
 320                 dump_spd_registers();
 321         }
 322 #endif
 323 #if 1
 324         show_dram_slots();
 325 #endif
 326         disable_watchdogs();
 327 //      dump_ipmi_registers();
 328         mainboard_set_e7520_leds();
 329
 330         sdram_initialize(ARRAY_SIZE(mch), mch);
 331 #if 0
 332         dump_pci_devices();
 333 #endif
 334 #if 1
 335         dump_pci_device(PCI_DEV(0, 0x00, 0));
 336 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 337 #endif
 338
 339 #if 1 // temporarily disabled
 340         /* Check the first 1M */
 341 //      ram_check(0x00000000, 0x000100000);
 342 //      ram_check(0x00000000, 0x000a0000);
 343 //      ram_check(0x00100000, 0x01000000);
 344         ram_check(0x00100000, 0x00100100);
 345         /* check the first 1M in the 3rd Gig */
 346 //      ram_check(0x30100000, 0x31000000);
 347 #endif
 348 #if 0
 349         ram_check(0x00000000, 0x02000000);
 350 #endif
 351
 352 #if 0
 353         while(1) {
 354                 hlt();
 355         }
 356 #endif
 357 }
 358