src/mainboard/dell/s1850/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "lib/ramtest.c"
  14 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  15 #include "northbridge/intel/e7520/raminit.h"
  16 #include "superio/nsc/pc8374/pc8374_early_serial.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "debug.c"
  20 #include "watchdog.c"
  21 #include "reset.c"
  22 #include "s1850_fixups.c"
  23 #include "northbridge/intel/e7520/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26
  27 #define SIO_GPIO_BASE 0x680
  28 #define SIO_XBUS_BASE 0x4880
  29
  30 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  31
  32 #define DEVPRES_CONFIG  ( \
  33         DEVPRES_D0F0 | \
  34         DEVPRES_D1F0 | \
  35         DEVPRES_D2F0 | \
  36         DEVPRES_D3F0 | \
  37         DEVPRES_D4F0 | \
  38         DEVPRES_D6F0 | \
  39         0 )
  40 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  41
  42 #define RECVENA_CONFIG  0x0808090a
  43 #define RECVENB_CONFIG  0x0808090a
  44
  45 //void udelay(int usecs)
  46 //{
  47 //        int i;
  48 //        for(i = 0; i < usecs; i++)
  49 //                outb(i&0xff, 0x80);
  50 //}
  51
  52 #if 0
  53 static void hard_reset(void)
  54 {
  55         /* enable cf9 */
  56         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  57         /* reset */
  58         outb(0x0e, 0x0cf9);
  59 }
  60 #endif
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66 static inline int spd_read_byte(unsigned device, unsigned address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #include "northbridge/intel/e7520/raminit.c"
  72 #include "lib/generic_sdram.c"
  73
  74
  75 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  76  */
  77
  78 #define nftransport  0xc
  79
  80 #define OBF  0
  81 #define IBF 1
  82
  83 #define ipmidata  0xca0
  84 #define ipmicsr  0xca4
  85
  86
  87 static inline void  ibfzero(void)
  88 {
  89         while(inb(ipmicsr) &  (1<<IBF))
  90                 ;
  91 }
  92 static inline void  clearobf(void)
  93 {
  94         (void) inb(ipmidata);
  95 }
  96
  97 static inline void  waitobf(void)
  98 {
  99         while((inb(ipmicsr) &  (1<<OBF)) == 0)
 100                 ;
 101 }
 102 /* quite possibly the stupidest interface ever designed. */
 103 static inline void  first_cmd_byte(unsigned char byte)
 104 {
 105         ibfzero();
 106         clearobf();
 107         outb(0x61, ipmicsr);
 108         ibfzero();
 109         clearobf();
 110         outb(byte, ipmidata);
 111 }
 112
 113 static inline void  next_cmd_byte(unsigned char byte)
 114 {
 115
 116         ibfzero();
 117         clearobf();
 118         outb(byte, ipmidata);
 119 }
 120
 121 static inline void  last_cmd_byte(unsigned char byte)
 122 {
 123         outb(0x62, ipmicsr);
 124
 125         ibfzero();
 126         clearobf();
 127         outb(byte,  ipmidata);
 128 }
 129
 130 static inline void read_response_byte(void)
 131 {
 132         int val = -1;
 133         if ((inb(ipmicsr)>>6) != 1)
 134                 return;
 135
 136         ibfzero();
 137         waitobf();
 138         val = inb(ipmidata);
 139         outb(0x68, ipmidata);
 140
 141         /* see if it is done */
 142         if ((inb(ipmicsr)>>6) != 1){
 143                 /* wait for the dummy read. Which describes this protocol */
 144                 waitobf();
 145                 (void)inb(ipmidata);
 146         }
 147 }
 148
 149 static inline void ipmidelay(void)
 150 {
 151         int i;
 152         for(i = 0; i < 1000; i++) {
 153                 inb(0x80);
 154         }
 155 }
 156
 157 static inline void bmc_foad(void)
 158 {
 159         unsigned char c;
 160         /* be safe; make sure it is really ready */
 161         while ((inb(ipmicsr)>>6)) {
 162                 outb(0x60, ipmicsr);
 163                 inb(ipmidata);
 164         }
 165         first_cmd_byte(nftransport << 2);
 166         ipmidelay();
 167         next_cmd_byte(0x12);
 168         ipmidelay();
 169         next_cmd_byte(2);
 170         ipmidelay();
 171         last_cmd_byte(3);
 172         ipmidelay();
 173 }
 174
 175 /* end IPMI garbage */
 176 static void main(unsigned long bist)
 177 {
 178         /*
 179          *
 180          *
 181          */
 182         static const struct mem_controller mch[] = {
 183                 {
 184                         .node_id = 0,
 185                         .f0 = PCI_DEV(0, 0x00, 0),
 186                         .f1 = PCI_DEV(0, 0x00, 1),
 187                         .f2 = PCI_DEV(0, 0x00, 2),
 188                         .f3 = PCI_DEV(0, 0x00, 3),
 189                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
 190                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
 191                 }
 192         };
 193
 194         if (bist == 0) {
 195                 /* Skip this if there was a built in self test failure */
 196                 early_mtrr_init();
 197                 if (memory_initialized()) {
 198                         asm volatile ("jmp __cpu_reset");
 199                 }
 200         }
 201         /* Setup the console */
 202         mainboard_set_ich5();
 203         bmc_foad();
 204         pc8374_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 205         uart_init();
 206         console_init();
 207
 208         /* Halt if there was a built in self test failure */
 209 //      report_bist_failure(bist);
 210
 211         /* MOVE ME TO A BETTER LOCATION !!! */
 212         /* config LPC decode for flash memory access */
 213         device_t dev;
 214         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 215         if (dev == PCI_DEV_INVALID) {
 216                 die("Missing ich5?");
 217         }
 218         pci_write_config32(dev, 0xe8, 0x00000000);
 219         pci_write_config8(dev, 0xf0, 0x00);
 220
 221 #if 0
 222         display_cpuid_update_microcode();
 223 #endif
 224 #if 1
 225         print_pci_devices();
 226 #endif
 227 #if 1
 228         enable_smbus();
 229 #endif
 230 #if 1
 231 //      dump_spd_registers(&cpu[0]);
 232         int i;
 233         for(i = 0; i < 1; i++) {
 234                 dump_spd_registers();
 235         }
 236 #endif
 237         disable_watchdogs();
 238 //      dump_ipmi_registers();
 239         mainboard_set_e7520_leds();
 240 //      memreset_setup();
 241         sdram_initialize(ARRAY_SIZE(mch), mch);
 242 #if 1
 243         dump_pci_devices();
 244 #endif
 245 #if 1
 246         dump_pci_device(PCI_DEV(0, 0x00, 0));
 247         dump_bar14(PCI_DEV(0, 0x00, 0));
 248 #endif
 249
 250 #if 1 // temporarily disabled
 251         /* Check the first 1M */
 252 //      ram_check(0x00000000, 0x000100000);
 253 //      ram_check(0x00000000, 0x000a0000);
 254 //      ram_check(0x00100000, 0x01000000);
 255         ram_check(0x00100000, 0x00100100);
 256         /* check the first 1M in the 3rd Gig */
 257 //      ram_check(0x30100000, 0x31000000);
 258 #endif
 259 #if 0
 260         ram_check(0x00000000, 0x02000000);
 261 #endif
 262
 263 #if 0
 264         while(1) {
 265                 hlt();
 266         }
 267 #endif
 268 }