src/mainboard/broadcom/blast/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  20 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  29
  30 #include "cpu/x86/mtrr/earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  36 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  37
  38 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  39
  40 static void memreset_setup(void)
  41 {
  42 }
  43
  44 static void memreset(int controllers, const struct mem_controller *ctrl)
  45 {
  46 }
  47
  48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  49 {
  50 #define SMBUS_HUB 0x71
  51         unsigned device=(ctrl->channel0[0])>>8;
  52         smbus_send_byte(SMBUS_HUB, device);
  53 }
  54
  55 #if 0
  56 static inline void change_i2c_mux(unsigned device)
  57 {
  58 #define SMBUS_HUB 0x71
  59         int ret;
  60         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  61         ret = smbus_send_byte(SMBUS_HUB, device);
  62         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
  63 }
  64 #endif
  65
  66 static inline int spd_read_byte(unsigned device, unsigned address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #include "northbridge/amd/amdk8/raminit.c"
  72 #include "northbridge/amd/amdk8/coherent_ht.c"
  73 #include "lib/generic_sdram.c"
  74
  75  /* tyan does not want the default */
  76 #include "resourcemap.c"
  77
  78 #include "cpu/amd/dualcore/dualcore.c"
  79
  80 #define RC0 (6<<8)
  81 #define RC1 (7<<8)
  82
  83 #define DIMM0 0x50
  84 #define DIMM1 0x51
  85 #define DIMM2 0x52
  86 #define DIMM3 0x53
  87
  88
  89 #include "cpu/amd/car/post_cache_as_ram.c"
  90
  91 #include "cpu/amd/model_fxx/init_cpus.c"
  92
  93 #include "northbridge/amd/amdk8/early_ht.c"
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const uint16_t spd_addr[] = {
  98                 RC0|DIMM0, RC0|DIMM2, 0, 0,
  99                 RC0|DIMM1, RC0|DIMM3, 0, 0,
 100                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 101                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 102         };
 103
 104         int needs_reset;
 105         unsigned bsp_apicid = 0;
 106
 107         struct mem_controller ctrl[8];
 108         unsigned nodes;
 109
 110         if (!cpu_init_detectedx && boot_cpu()) {
 111                 /* Nothing special needs to be done to find bus 0 */
 112                 /* Allow the HT devices to be found */
 113
 114                 enumerate_ht_chain();
 115
 116                 bcm5785_enable_rom();
 117
 118                 bcm5785_enable_lpc();
 119
 120                 //enable RTC
 121                 pc87417_enable_dev(RTC_DEV);
 122         }
 123
 124         if (bist == 0) {
 125                 bsp_apicid = init_cpus(cpu_init_detectedx);
 126         }
 127 //      post_code(0x32);
 128
 129         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 130 //      post_code(0x33);
 131
 132         uart_init();
 133 //      post_code(0x34);
 134
 135         console_init();
 136
 137         /* Halt if there was a built in self test failure */
 138         report_bist_failure(bist);
 139
 140         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 141
 142         setup_blast_resource_map();
 143
 144 #if 0
 145         dump_pci_device(PCI_DEV(0, 0x18, 0));
 146         dump_pci_device(PCI_DEV(0, 0x19, 0));
 147 #endif
 148
 149         needs_reset = setup_coherent_ht_domain();
 150
 151 #if CONFIG_LOGICAL_CPUS==1
 152         // It is said that we should start core1 after all core0 launched
 153         wait_all_core0_started();
 154         start_other_cores();
 155 #endif
 156         wait_all_aps_started(bsp_apicid);
 157
 158         needs_reset |= ht_setup_chains_x();
 159
 160         bcm5785_early_setup();
 161
 162         if (needs_reset) {
 163                 print_info("ht reset -\n");
 164                 soft_reset();
 165         }
 166
 167         allow_all_aps_stop(bsp_apicid);
 168
 169         nodes = get_nodes();
 170         //It's the time to set ctrl now;
 171         fill_mem_ctrl(nodes, ctrl, spd_addr);
 172
 173         enable_smbus();
 174
 175 #if 0
 176         int i;
 177         for(i=4;i<8;i++) {
 178                 change_i2c_mux(i);
 179                 dump_smbus_registers();
 180         }
 181 #endif
 182
 183         memreset_setup();
 184
 185 //      init_timer();
 186
 187         sdram_initialize(nodes, ctrl);
 188
 189 #if 0
 190         print_pci_devices();
 191 #endif
 192
 193 #if 0
 194         dump_pci_devices();
 195 #endif
 196
 197         post_cache_as_ram();
 198
 199 }
 200