src/mainboard/broadcom/blast/romstage.c

   1
   2 #if CONFIG_LOGICAL_CPUS==1
   3 #define SET_NB_CFG_54 1
   4 #endif
   5
   6 #include <stdint.h>
   7 #include <string.h>
   8 #include <device/pci_def.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  19 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  28
  29 #include "cpu/x86/mtrr/earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #include "northbridge/amd/amdk8/setup_resource_map.c"
  33
  34 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  35 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  36
  37 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  38
  39 static void memreset_setup(void)
  40 {
  41 }
  42
  43 static void memreset(int controllers, const struct mem_controller *ctrl)
  44 {
  45 }
  46
  47 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  48 {
  49 #define SMBUS_HUB 0x71
  50         unsigned device=(ctrl->channel0[0])>>8;
  51         smbus_send_byte(SMBUS_HUB, device);
  52 }
  53
  54 #if 0
  55 static inline void change_i2c_mux(unsigned device)
  56 {
  57 #define SMBUS_HUB 0x71
  58         int ret;
  59         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  60         ret = smbus_send_byte(SMBUS_HUB, device);
  61         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
  62 }
  63 #endif
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70 #include "northbridge/amd/amdk8/raminit.c"
  71 #include "northbridge/amd/amdk8/coherent_ht.c"
  72 #include "lib/generic_sdram.c"
  73
  74  /* tyan does not want the default */
  75 #include "resourcemap.c"
  76
  77 #include "cpu/amd/dualcore/dualcore.c"
  78
  79 #define RC0 (6<<8)
  80 #define RC1 (7<<8)
  81
  82 #define DIMM0 0x50
  83 #define DIMM1 0x51
  84 #define DIMM2 0x52
  85 #define DIMM3 0x53
  86
  87
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         static const uint16_t spd_addr[] = {
  97                 RC0|DIMM0, RC0|DIMM2, 0, 0,
  98                 RC0|DIMM1, RC0|DIMM3, 0, 0,
  99                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 100                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 101         };
 102
 103         int needs_reset;
 104         unsigned bsp_apicid = 0;
 105
 106         struct mem_controller ctrl[8];
 107         unsigned nodes;
 108
 109         if (!cpu_init_detectedx && boot_cpu()) {
 110                 /* Nothing special needs to be done to find bus 0 */
 111                 /* Allow the HT devices to be found */
 112
 113                 enumerate_ht_chain();
 114
 115                 bcm5785_enable_rom();
 116
 117                 bcm5785_enable_lpc();
 118
 119                 //enable RTC
 120                 pc87417_enable_dev(RTC_DEV);
 121         }
 122
 123         if (bist == 0) {
 124                 bsp_apicid = init_cpus(cpu_init_detectedx);
 125         }
 126 //      post_code(0x32);
 127
 128         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 129 //      post_code(0x33);
 130
 131         uart_init();
 132 //      post_code(0x34);
 133
 134         console_init();
 135
 136         /* Halt if there was a built in self test failure */
 137         report_bist_failure(bist);
 138
 139         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 140
 141         setup_blast_resource_map();
 142
 143 #if 0
 144         dump_pci_device(PCI_DEV(0, 0x18, 0));
 145         dump_pci_device(PCI_DEV(0, 0x19, 0));
 146 #endif
 147
 148         needs_reset = setup_coherent_ht_domain();
 149
 150 #if CONFIG_LOGICAL_CPUS==1
 151         // It is said that we should start core1 after all core0 launched
 152         wait_all_core0_started();
 153         start_other_cores();
 154 #endif
 155         wait_all_aps_started(bsp_apicid);
 156
 157         needs_reset |= ht_setup_chains_x();
 158
 159         bcm5785_early_setup();
 160
 161         if (needs_reset) {
 162                 print_info("ht reset -\n");
 163                 soft_reset();
 164         }
 165
 166         allow_all_aps_stop(bsp_apicid);
 167
 168         nodes = get_nodes();
 169         //It's the time to set ctrl now;
 170         fill_mem_ctrl(nodes, ctrl, spd_addr);
 171
 172         enable_smbus();
 173
 174 #if 0
 175         int i;
 176         for(i=4;i<8;i++) {
 177                 change_i2c_mux(i);
 178                 dump_smbus_registers();
 179         }
 180 #endif
 181
 182         memreset_setup();
 183
 184 //      init_timer();
 185
 186         sdram_initialize(nodes, ctrl);
 187
 188 #if 0
 189         print_pci_devices();
 190 #endif
 191
 192 #if 0
 193         dump_pci_devices();
 194 #endif
 195
 196         post_cache_as_ram();
 197
 198 }
 199