3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
11 #include <cpu/amd/model_fxx_rev.h>
12 #include "northbridge/amd/amdk8/incoherent_ht.c"
13 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
14 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
15 #include "northbridge/amd/amdk8/raminit.h"
16 #include "cpu/amd/model_fxx/apic_timer.c"
17 #include "lib/delay.c"
19 #include "cpu/x86/lapic/boot_cpu.c"
20 #include "northbridge/amd/amdk8/reset_test.c"
21 #include "northbridge/amd/amdk8/debug.c"
22 #include "superio/nsc/pc87417/pc87417_early_serial.c"
24 #include "cpu/x86/mtrr/earlymtrr.c"
25 #include "cpu/x86/bist.h"
27 #include "northbridge/amd/amdk8/setup_resource_map.c"
29 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
30 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
32 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
34 static void memreset_setup(void)
38 static void memreset(int controllers, const struct mem_controller *ctrl)
42 static inline void activate_spd_rom(const struct mem_controller *ctrl)
44 #define SMBUS_HUB 0x71
45 unsigned device=(ctrl->channel0[0])>>8;
46 smbus_send_byte(SMBUS_HUB, device);
50 static inline void change_i2c_mux(unsigned device)
52 #define SMBUS_HUB 0x71
54 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
55 ret = smbus_send_byte(SMBUS_HUB, device);
56 print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
60 static inline int spd_read_byte(unsigned device, unsigned address)
62 return smbus_read_byte(device, address);
65 #include "northbridge/amd/amdk8/raminit.c"
66 #include "northbridge/amd/amdk8/coherent_ht.c"
67 #include "lib/generic_sdram.c"
69 /* tyan does not want the default */
70 #include "resourcemap.c"
72 #include "cpu/amd/dualcore/dualcore.c"
78 #include "cpu/amd/car/post_cache_as_ram.c"
80 #include "cpu/amd/model_fxx/init_cpus.c"
82 #include "northbridge/amd/amdk8/early_ht.c"
84 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
86 static const uint16_t spd_addr[] = {
87 RC0|DIMM0, RC0|DIMM2, 0, 0,
88 RC0|DIMM1, RC0|DIMM3, 0, 0,
89 RC1|DIMM0, RC1|DIMM2, 0, 0,
90 RC1|DIMM1, RC1|DIMM3, 0, 0,
94 unsigned bsp_apicid = 0;
96 struct mem_controller ctrl[8];
99 if (!cpu_init_detectedx && boot_cpu()) {
100 /* Nothing special needs to be done to find bus 0 */
101 /* Allow the HT devices to be found */
103 enumerate_ht_chain();
105 bcm5785_enable_rom();
107 bcm5785_enable_lpc();
110 pc87417_enable_dev(RTC_DEV);
114 bsp_apicid = init_cpus(cpu_init_detectedx);
118 pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
126 /* Halt if there was a built in self test failure */
127 report_bist_failure(bist);
129 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
131 setup_blast_resource_map();
134 dump_pci_device(PCI_DEV(0, 0x18, 0));
135 dump_pci_device(PCI_DEV(0, 0x19, 0));
138 needs_reset = setup_coherent_ht_domain();
140 #if CONFIG_LOGICAL_CPUS==1
141 // It is said that we should start core1 after all core0 launched
142 wait_all_core0_started();
145 wait_all_aps_started(bsp_apicid);
147 needs_reset |= ht_setup_chains_x();
149 bcm5785_early_setup();
152 print_info("ht reset -\n");
156 allow_all_aps_stop(bsp_apicid);
159 //It's the time to set ctrl now;
160 fill_mem_ctrl(nodes, ctrl, spd_addr);
168 dump_smbus_registers();
176 sdram_initialize(nodes, ctrl);