1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
4 #include <device/pci.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
11 #include <cpu/amd/amdk8_sysconf.h>
13 extern unsigned char bus_isa;
14 extern unsigned char bus_bcm5780[7];
15 extern unsigned char bus_bcm5785_0;
16 extern unsigned char bus_bcm5785_1;
17 extern unsigned char bus_bcm5785_1_1;
18 extern unsigned apicid_bcm5785[3];
20 extern unsigned sbdn2;
24 static void *smp_write_config_table(void *v)
26 static const char sig[4] = "PCMP";
27 static const char oem[8] = "COREBOOT";
28 static const char productid[12] = "BLAST ";
29 struct mp_config_table *mc;
31 unsigned char bus_num;
34 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
35 memset(mc, 0, sizeof(*mc));
37 memcpy(mc->mpc_signature, sig, sizeof(sig));
38 mc->mpc_length = sizeof(*mc); /* initially just the header */
40 mc->mpc_checksum = 0; /* not yet computed */
41 memcpy(mc->mpc_oem, oem, sizeof(oem));
42 memcpy(mc->mpc_productid, productid, sizeof(productid));
45 mc->mpc_entry_count = 0; /* No entries yet... */
46 mc->mpc_lapic = LAPIC_ADDR;
51 smp_write_processors(mc);
56 /* define bus and isa numbers */
57 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
58 smp_write_bus(mc, bus_num, "PCI ");
60 smp_write_bus(mc, bus_isa, "ISA ");
62 /*I/O APICs: APIC ID Version State Address*/
67 dev = dev_find_device(0x1166, 0x0235, dev);
69 res = find_resource(dev, PCI_BASE_ADDRESS_0);
71 smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base);
78 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
79 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x0);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x2);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_bcm5785[0], 0x3);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_bcm5785[0], 0x4);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, apicid_bcm5785[0], 0x5);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_bcm5785[0], 0x6);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_bcm5785[0], 0x7);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_bcm5785[0], 0x8);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_bcm5785[0], 0x9);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_bcm5785[0], 0xc);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_bcm5785[0], 0xd);
93 outb(0x02, 0xc00); outb(0x0e, 0xc01);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
98 outb(0x07, 0xc00); outb(0x0f, 0xc01);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
102 outb(0x01, 0xc00); outb(0x0a, 0xc01);
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
110 /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
113 dev = dev_find_device(0x1166, 0x0205, 0);
116 dword = pci_read_config32(dev, 0x6c);
117 dword |= (1<<4); // enable interrupts
118 pci_write_config32(dev, 0x6c, dword);
124 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
130 //pci slot (on bcm5785)
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); //
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); //
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); //
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); //
171 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
172 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
173 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
174 /* There is no extension information... */
176 /* Compute the checksums */
177 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
178 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
179 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
180 mc, smp_next_mpe_entry(mc));
181 return smp_next_mpe_entry(mc);
184 unsigned long write_smp_table(unsigned long addr)
187 v = smp_write_floating_table(addr);
188 return (unsigned long)smp_write_config_table(v);