1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
4 #include <device/pci.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
10 #include <cpu/amd/amdk8_sysconf.h>
12 extern unsigned char bus_isa;
13 extern unsigned char bus_bcm5780[7];
14 extern unsigned char bus_bcm5785_0;
15 extern unsigned char bus_bcm5785_1;
16 extern unsigned char bus_bcm5785_1_1;
17 extern unsigned apicid_bcm5785[3];
19 extern unsigned sbdn2;
21 static void *smp_write_config_table(void *v)
23 struct mp_config_table *mc;
24 unsigned char bus_num;
27 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
29 mptable_init(mc, "BLAST ", LAPIC_ADDR);
31 smp_write_processors(mc);
36 /* define bus and isa numbers */
37 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
38 smp_write_bus(mc, bus_num, "PCI ");
40 smp_write_bus(mc, bus_isa, "ISA ");
42 /*I/O APICs: APIC ID Version State Address*/
47 dev = dev_find_device(0x1166, 0x0235, dev);
49 res = find_resource(dev, PCI_BASE_ADDRESS_0);
51 smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base);
58 mptable_add_isa_interrupts(mc, bus_isa, apicid_bcm5785[0], 0);
61 outb(0x02, 0xc00); outb(0x0e, 0xc01);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
66 outb(0x07, 0xc00); outb(0x0f, 0xc01);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
70 outb(0x01, 0xc00); outb(0x0a, 0xc01);
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
78 /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
81 dev = dev_find_device(0x1166, 0x0205, 0);
84 dword = pci_read_config32(dev, 0x6c);
85 dword |= (1<<4); // enable interrupts
86 pci_write_config32(dev, 0x6c, dword);
92 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
98 //pci slot (on bcm5785)
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); //
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); //
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); //
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); //
139 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
140 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
141 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
142 /* There is no extension information... */
144 /* Compute the checksums */
145 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
146 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
147 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
148 mc, smp_next_mpe_entry(mc));
149 return smp_next_mpe_entry(mc);
152 unsigned long write_smp_table(unsigned long addr)
155 v = smp_write_floating_table(addr);
156 return (unsigned long)smp_write_config_table(v);