src/mainboard/broadcom/blast/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #define SET_NB_CFG_54 1
   8 #endif
   9
  10 #include <stdint.h>
  11 #include <string.h>
  12 #include <device/pci_def.h>
  13 #include <arch/io.h>
  14 #include <device/pnp_def.h>
  15 #include <arch/romcc_io.h>
  16 #include <cpu/x86/lapic.h>
  17 #include "option_table.h"
  18 #include "pc80/mc146818rtc_early.c"
  19 #include "pc80/serial.c"
  20 #include "arch/i386/lib/console.c"
  21 #include "lib/ramtest.c"
  22
  23 #if 0
  24 static void post_code(uint8_t value) {
  25 #if 0
  26         int i;
  27         for(i=0;i<0x80000;i++) {
  28                 outb(value, 0x80);
  29         }
  30 #endif
  31 }
  32 #endif
  33
  34 #include <cpu/amd/model_fxx_rev.h>
  35 #include "northbridge/amd/amdk8/incoherent_ht.c"
  36 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40
  41 #include "cpu/x86/lapic/boot_cpu.c"
  42 #include "northbridge/amd/amdk8/reset_test.c"
  43 #include "northbridge/amd/amdk8/debug.c"
  44 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  45
  46 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  52 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  53
  54 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  55
  56 static void memreset_setup(void)
  57 {
  58 }
  59
  60 static void memreset(int controllers, const struct mem_controller *ctrl)
  61 {
  62 }
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66 #define SMBUS_HUB 0x71
  67         int ret,i;
  68         unsigned device=(ctrl->channel0[0])>>8;
  69         smbus_send_byte(SMBUS_HUB, device);
  70 }
  71 #if 0
  72 static inline void change_i2c_mux(unsigned device)
  73 {
  74 #define SMBUS_HUB 0x71
  75         int ret;
  76         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
  77         ret = smbus_send_byte(SMBUS_HUB, device);
  78         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n");
  79 }
  80 #endif
  81
  82 static inline int spd_read_byte(unsigned device, unsigned address)
  83 {
  84         return smbus_read_byte(device, address);
  85 }
  86
  87 #include "northbridge/amd/amdk8/raminit.c"
  88 #include "northbridge/amd/amdk8/coherent_ht.c"
  89 #include "lib/generic_sdram.c"
  90
  91  /* tyan does not want the default */
  92 #include "resourcemap.c"
  93
  94 #include "cpu/amd/dualcore/dualcore.c"
  95
  96 #define RC0 (6<<8)
  97 #define RC1 (7<<8)
  98
  99 #define DIMM0 0x50
 100 #define DIMM1 0x51
 101 #define DIMM2 0x52
 102 #define DIMM3 0x53
 103
 104 #include "cpu/amd/car/copy_and_run.c"
 105 #include "cpu/amd/car/post_cache_as_ram.c"
 106
 107 #include "cpu/amd/model_fxx/init_cpus.c"
 108
 109
 110 #if CONFIG_USE_FALLBACK_IMAGE == 1
 111
 112 #include "northbridge/amd/amdk8/early_ht.c"
 113
 114 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 115 {
 116
 117
 118         /* Is this a cpu only reset? Is this a secondary cpu? */
 119         if ((cpu_init_detectedx) || (!boot_cpu())) {
 120                 if (last_boot_normal()) { // RTC already inited
 121                         goto normal_image;
 122                 } else {
 123                         goto fallback_image;
 124                 }
 125         }
 126         /* Nothing special needs to be done to find bus 0 */
 127         /* Allow the HT devices to be found */
 128
 129         enumerate_ht_chain();
 130
 131         bcm5785_enable_rom();
 132
 133         bcm5785_enable_lpc();
 134
 135         //enable RTC
 136         pc87417_enable_dev(RTC_DEV);
 137
 138         /* Is this a deliberate reset by the bios */
 139 //        post_code(0x22);
 140         if (bios_reset_detected() && last_boot_normal()) {
 141                 goto normal_image;
 142         }
 143         /* This is the primary cpu how should I boot? */
 144         else if (do_normal_boot()) {
 145                 goto normal_image;
 146         }
 147         else {
 148                 goto fallback_image;
 149         }
 150  normal_image:
 151 //        post_code(0x23);
 152         __asm__ volatile ("jmp __normal_image"
 153                 : /* outputs */
 154                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 155                 );
 156
 157  fallback_image:
 158 //        post_code(0x25);
 159         ;
 160 }
 161 #endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
 162
 163 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 164
 165 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 166 {
 167
 168 #if CONFIG_USE_FALLBACK_IMAGE == 1
 169         failover_process(bist, cpu_init_detectedx);
 170 #endif
 171         real_main(bist, cpu_init_detectedx);
 172
 173 }
 174
 175 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 176 {
 177         static const uint16_t spd_addr[] = {
 178                 RC0|DIMM0, RC0|DIMM2, 0, 0,
 179                 RC0|DIMM1, RC0|DIMM3, 0, 0,
 180 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 181                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 182                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 183 #endif
 184         };
 185
 186         int needs_reset;
 187         unsigned bsp_apicid = 0;
 188
 189         struct mem_controller ctrl[8];
 190         unsigned nodes;
 191
 192         if (bist == 0) {
 193                 bsp_apicid = init_cpus(cpu_init_detectedx);
 194         }
 195 //      post_code(0x32);
 196
 197         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 198 //      post_code(0x33);
 199
 200         uart_init();
 201 //      post_code(0x34);
 202
 203         console_init();
 204
 205         /* Halt if there was a built in self test failure */
 206         report_bist_failure(bist);
 207
 208         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 209
 210         setup_blast_resource_map();
 211
 212 #if 0
 213         dump_pci_device(PCI_DEV(0, 0x18, 0));
 214         dump_pci_device(PCI_DEV(0, 0x19, 0));
 215 #endif
 216
 217         needs_reset = setup_coherent_ht_domain();
 218
 219 #if CONFIG_LOGICAL_CPUS==1
 220         // It is said that we should start core1 after all core0 launched
 221         wait_all_core0_started();
 222         start_other_cores();
 223 #endif
 224         wait_all_aps_started(bsp_apicid);
 225
 226         needs_reset |= ht_setup_chains_x();
 227
 228         bcm5785_early_setup();
 229
 230         if (needs_reset) {
 231                 print_info("ht reset -\r\n");
 232                 soft_reset();
 233         }
 234
 235         allow_all_aps_stop(bsp_apicid);
 236
 237         nodes = get_nodes();
 238         //It's the time to set ctrl now;
 239         fill_mem_ctrl(nodes, ctrl, spd_addr);
 240
 241         enable_smbus();
 242
 243 #if 0
 244         int i;
 245         for(i=4;i<8;i++) {
 246                 change_i2c_mux(i);
 247                 dump_smbus_registers();
 248         }
 249 #endif
 250
 251         memreset_setup();
 252
 253 //      init_timer();
 254
 255         sdram_initialize(nodes, ctrl);
 256
 257 #if 0
 258         print_pci_devices();
 259 #endif
 260
 261 #if 0
 262         dump_pci_devices();
 263 #endif
 264
 265         post_cache_as_ram();
 266
 267 }