src/mainboard/broadcom/blast/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4
   5 //#define K8_SCAN_PCI_BUS 1
   6
   7 #define K8_4RANK_DIMM_SUPPORT 1
   8
   9 #if CONFIG_LOGICAL_CPUS==1
  10 #define SET_NB_CFG_54 1
  11 #endif
  12
  13 #include <stdint.h>
  14 #include <device/pci_def.h>
  15 #include <arch/io.h>
  16 #include <device/pnp_def.h>
  17 #include <arch/romcc_io.h>
  18 #include <cpu/x86/lapic.h>
  19 #include "option_table.h"
  20 #include "pc80/mc146818rtc_early.c"
  21 #include "pc80/serial.c"
  22 #include "arch/i386/lib/console.c"
  23 #include "ram/ramtest.c"
  24
  25 #if 0
  26 static void post_code(uint8_t value) {
  27 #if 0
  28         int i;
  29         for(i=0;i<0x80000;i++) {
  30                 outb(value, 0x80);
  31         }
  32 #endif
  33 }
  34 #endif
  35
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include "northbridge/amd/amdk8/incoherent_ht.c"
  38 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  39 #include "northbridge/amd/amdk8/raminit.h"
  40 #include "cpu/amd/model_fxx/apic_timer.c"
  41 #include "lib/delay.c"
  42
  43 #if CONFIG_USE_INIT == 0
  44 #include "lib/memcpy.c"
  45 #endif
  46
  47 #include "cpu/x86/lapic/boot_cpu.c"
  48 #include "northbridge/amd/amdk8/reset_test.c"
  49 #include "northbridge/amd/amdk8/debug.c"
  50 #include "superio/NSC/pc87417/pc87417_early_serial.c"
  51
  52 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  53 #include "cpu/x86/bist.h"
  54
  55 #include "northbridge/amd/amdk8/setup_resource_map.c"
  56
  57 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  58 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  59
  60 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  61
  62 static void memreset_setup(void)
  63 {
  64 }
  65
  66 static void memreset(int controllers, const struct mem_controller *ctrl)
  67 {
  68 }
  69
  70 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  71 {
  72 #define SMBUS_HUB 0x71
  73         int ret,i;
  74         unsigned device=(ctrl->channel0[0])>>8;
  75         smbus_send_byte(SMBUS_HUB, device);
  76 }
  77 #if 0
  78 static inline void change_i2c_mux(unsigned device)
  79 {
  80 #define SMBUS_HUB 0x71
  81         int ret;
  82         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
  83         ret = smbus_send_byte(SMBUS_HUB, device);
  84         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n");
  85 }
  86 #endif
  87
  88 static inline int spd_read_byte(unsigned device, unsigned address)
  89 {
  90         return smbus_read_byte(device, address);
  91 }
  92
  93 #include "northbridge/amd/amdk8/raminit.c"
  94 #include "northbridge/amd/amdk8/coherent_ht.c"
  95 #include "sdram/generic_sdram.c"
  96
  97  /* tyan does not want the default */
  98 #include "resourcemap.c"
  99
 100 #include "cpu/amd/dualcore/dualcore.c"
 101
 102 #define RC0 (6<<8)
 103 #define RC1 (7<<8)
 104
 105 #define DIMM0 0x50
 106 #define DIMM1 0x51
 107 #define DIMM2 0x52
 108 #define DIMM3 0x53
 109
 110 #include "cpu/amd/car/copy_and_run.c"
 111 #include "cpu/amd/car/post_cache_as_ram.c"
 112
 113 #include "cpu/amd/model_fxx/init_cpus.c"
 114
 115
 116 #if USE_FALLBACK_IMAGE == 1
 117
 118 #include "northbridge/amd/amdk8/early_ht.c"
 119
 120 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 121 {
 122
 123
 124         /* Is this a cpu only reset? Is this a secondary cpu? */
 125         if ((cpu_init_detectedx) || (!boot_cpu())) {
 126                 if (last_boot_normal()) { // RTC already inited
 127                         goto normal_image;
 128                 } else {
 129                         goto fallback_image;
 130                 }
 131         }
 132         /* Nothing special needs to be done to find bus 0 */
 133         /* Allow the HT devices to be found */
 134
 135         enumerate_ht_chain();
 136
 137         bcm5785_enable_rom();
 138
 139         bcm5785_enable_lpc();
 140
 141         //enable RTC
 142         pc87417_enable_dev(RTC_DEV);
 143
 144         /* Is this a deliberate reset by the bios */
 145 //        post_code(0x22);
 146         if (bios_reset_detected() && last_boot_normal()) {
 147                 goto normal_image;
 148         }
 149         /* This is the primary cpu how should I boot? */
 150         else if (do_normal_boot()) {
 151                 goto normal_image;
 152         }
 153         else {
 154                 goto fallback_image;
 155         }
 156  normal_image:
 157 //        post_code(0x23);
 158         __asm__ volatile ("jmp __normal_image"
 159                 : /* outputs */
 160                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 161                 );
 162
 163  fallback_image:
 164 //        post_code(0x25);
 165         ;
 166 }
 167 #endif /* USE_FALLBACK_IMAGE == 1 */
 168
 169 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 170
 171 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 172 {
 173
 174 #if USE_FALLBACK_IMAGE == 1
 175         failover_process(bist, cpu_init_detectedx);
 176 #endif
 177         real_main(bist, cpu_init_detectedx);
 178
 179 }
 180
 181 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 182 {
 183         static const uint16_t spd_addr[] = {
 184                 RC0|DIMM0, RC0|DIMM2, 0, 0,
 185                 RC0|DIMM1, RC0|DIMM3, 0, 0,
 186 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 187                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 188                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 189 #endif
 190         };
 191
 192         int needs_reset;
 193         unsigned cpu_reset = 0;
 194         unsigned bsp_apicid = 0;
 195
 196         struct mem_controller ctrl[8];
 197         unsigned nodes;
 198
 199         if (bist == 0) {
 200                 bsp_apicid = init_cpus(cpu_init_detectedx);
 201         }
 202 //      post_code(0x32);
 203
 204         pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE);
 205 //      post_code(0x33);
 206
 207         uart_init();
 208 //      post_code(0x34);
 209
 210         console_init();
 211
 212         /* Halt if there was a built in self test failure */
 213         report_bist_failure(bist);
 214
 215         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 216
 217         setup_blast_resource_map();
 218
 219 #if 0
 220         dump_pci_device(PCI_DEV(0, 0x18, 0));
 221         dump_pci_device(PCI_DEV(0, 0x19, 0));
 222 #endif
 223
 224         needs_reset = setup_coherent_ht_domain();
 225
 226 #if CONFIG_LOGICAL_CPUS==1
 227         // It is said that we should start core1 after all core0 launched
 228         wait_all_core0_started();
 229         start_other_cores();
 230 #endif
 231         wait_all_aps_started(bsp_apicid);
 232
 233         needs_reset |= ht_setup_chains_x();
 234
 235         bcm5785_early_setup();
 236
 237         if (needs_reset) {
 238                 print_info("ht reset -\r\n");
 239                 soft_reset();
 240         }
 241
 242         allow_all_aps_stop(bsp_apicid);
 243
 244         nodes = get_nodes();
 245         //It's the time to set ctrl now;
 246         fill_mem_ctrl(nodes, ctrl, spd_addr);
 247
 248         enable_smbus();
 249
 250 #if 0
 251         int i;
 252         for(i=4;i<8;i++) {
 253                 change_i2c_mux(i);
 254                 dump_smbus_registers();
 255         }
 256 #endif
 257
 258         memreset_setup();
 259
 260 //      init_timer();
 261
 262         sdram_initialize(nodes, ctrl);
 263
 264 #if 0
 265         print_pci_devices();
 266 #endif
 267
 268 #if 0
 269         dump_pci_devices();
 270 #endif
 271
 272         post_cache_as_ram(cpu_reset);
 273
 274 }