src/mainboard/bitworks/ims/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/hlt.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 #include "southbridge/intel/i440bx/i440bx_early_smbus.c"
  13 #include "superio/NSC/pc87351/pc87351_early_serial.c"
  14 #include "northbridge/intel/i440bx/raminit.h"
  15 #include "cpu/x86/mtrr/earlymtrr.c"
  16 #include "cpu/x86/bist.h"
  17
  18 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
  19
  20 /*
  21  */
  22 void udelay(int usecs)
  23 {
  24         int i;
  25         for(i = 0; i < usecs; i++)
  26                 outb(i&0xff, 0x80);
  27 }
  28
  29 #include "debug.c"
  30 #include "lib/delay.c"
  31
  32
  33 static void memreset_setup(void)
  34 {
  35 }
  36
  37 /*
  38   static void memreset(int controllers, const struct mem_controller *ctrl)
  39   {
  40   }
  41 */
  42
  43
  44 static void enable_mainboard_devices(void)
  45 {
  46         device_t dev;
  47         /* dev 0 for southbridge */
  48
  49         dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
  50
  51         if (dev == PCI_DEV_INVALID) {
  52                 die("Southbridge not found!!!\n");
  53         }
  54         pci_write_config8(dev, 0x50, 7);
  55         pci_write_config8(dev, 0x51, 0xff);
  56 #if 0
  57         // This early setup switches IDE into compatibility mode before PCI gets
  58         // // a chance to assign I/Os
  59         //         movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  60         //         //      movb    $0x09, %dl
  61         //                 movb    $0x00, %dl
  62         //                         PCI_WRITE_CONFIG_BYTE
  63         //
  64 #endif
  65         /* we do this here as in V2, we can not yet do raw operations
  66          * to pci!
  67          */
  68         dev += 0x100; /* ICKY */
  69
  70         pci_write_config8(dev, 0x42, 0);
  71 }
  72
  73 static void enable_shadow_ram(void)
  74 {
  75         device_t dev = 0; /* no need to look up 0:0.0 */
  76         unsigned char shadowreg;
  77         /* dev 0 for southbridge */
  78         shadowreg = pci_read_config8(dev, 0x63);
  79         /* 0xf0000-0xfffff */
  80         shadowreg |= 0x30;
  81         pci_write_config8(dev, 0x63, shadowreg);
  82 }
  83
  84 static inline int spd_read_byte(unsigned device, unsigned address)
  85 {
  86         unsigned char c;
  87         c = smbus_read_byte(device, address);
  88         return c;
  89 }
  90
  91
  92 #include "northbridge/intel/i440bx/raminit.c"
  93 #include "northbridge/intel/i440bx/debug.c"
  94 #include "sdram/generic_sdram.c"
  95
  96 static void main(unsigned long bist)
  97 {
  98         static const struct mem_controller cpu[] = {
  99                 {
 100                  .channel0 = {
 101                          (0xa << 3) | 0,
 102                          (0xa << 3) | 1,
 103                          (0xa << 3) | 2, (0xa << 3) | 3,
 104                         },
 105                  }
 106         };
 107         unsigned long x;
 108
 109         if (bist == 0) {
 110                 early_mtrr_init();
 111         }
 112         pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
 113         uart_init();
 114         console_init();
 115
 116         /* Halt if there was a built in self test failure */
 117         report_bist_failure(bist);
 118
 119         enable_smbus();
 120         dump_spd_registers(&cpu[0]);
 121
 122 #if 0
 123         enable_shadow_ram();
 124         /*
 125           memreset_setup();
 126           this is way more generic than we need.
 127           sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 128         */
 129         sdram_set_registers((const struct mem_controller *) 0);
 130         sdram_set_spd_registers((const struct mem_controller *) 0);
 131         sdram_enable(0, (const struct mem_controller *) 0);
 132 #endif
 133
 134         /* Check all of memory */
 135 #if 0
 136         ram_check(0x00000000, msr.lo);
 137 #endif
 138 #if 0
 139         static const struct {
 140                 unsigned long lo, hi;
 141         } check_addrs[] = {
 142                 /* Check 16MB of memory @ 0*/
 143                 { 0x00000000, 0x01000000 },
 144 #if TOTAL_CPUS > 1
 145                 /* Check 16MB of memory @ 2GB */
 146                 { 0x80000000, 0x81000000 },
 147 #endif
 148         };
 149         int i;
 150         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 151                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 152         }
 153 #endif
 154 }