1 chip northbridge/via/cn700 # Northbridge
2 device pci_domain 0 on # PCI domain
3 device pci 0.0 on end # AGP Bridge
4 device pci 0.1 on end # Error Reporting
5 device pci 0.2 on end # Host Bus Control
6 device pci 0.3 on end # Memory Controller
7 device pci 0.4 on end # Power Management
8 device pci 0.7 on end # V-Link Controller
9 device pci 1.0 on end # PCI Bridge
10 chip southbridge/via/vt8237r # Southbridge
11 # Enable both IDE channels.
12 register "ide0_enable" = "1"
13 register "ide1_enable" = "1"
14 # Both cables are 40pin.
15 register "ide0_80pin_cable" = "0"
16 register "ide1_80pin_cable" = "0"
17 register "fn_ctrl_lo" = "0x80"
18 register "fn_ctrl_hi" = "0x1d"
19 device pci f.0 on end # IDE
20 device pci 10.0 on end # UHCI
21 device pci 10.1 on end # UHCI
22 device pci 10.2 on end # UHCI
23 device pci 10.3 on end # UHCI
24 device pci 10.4 on end # EHCI
25 device pci 11.0 on # Southbridge LPC
26 chip superio/winbond/w83697hf # Super I/O
27 device pnp 2e.0 off # Floppy
32 device pnp 2e.1 on # Parallel Port
37 device pnp 2e.2 on # COM1
41 device pnp 2e.3 on # COM2
45 device pnp 2e.6 off end # Consumer IR
46 device pnp 2e.7 off end # Game port, GPIO 1
47 device pnp 2e.8 off end # MIDI port, GPIO 5
48 device pnp 2e.9 off end # GPIO 2-4
49 device pnp 2e.a off end # ACPI
50 device pnp 2e.b on # HWM
55 device pci 11.5 on end # AC'97 audio
56 device pci 12.0 on end # Ethernet
59 device lapic_cluster 0 on # APIC cluster
60 chip cpu/via/model_c7 # VIA C7
61 device lapic 0 on end # APIC