2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
26 #include <SBPLATFORM.h>
27 #include <cpu/amd/amdfam10_sysconf.h>
30 extern u8 bus_rs780[11];
31 extern u8 bus_sb800[2];
32 extern u32 apicid_sb800;
33 extern u32 bus_type[256];
34 extern u32 sbdn_rs780;
35 extern u32 sbdn_sb800;
38 [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
39 [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
40 [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
41 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
43 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
47 static void *smp_write_config_table(void *v)
49 struct mp_config_table *mc;
53 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
55 mptable_init(mc, LAPIC_ADDR);
57 smp_write_processors(mc);
61 mptable_write_buses(mc, NULL, &bus_isa);
63 /* I/O APICs: APIC ID Version State Address */
64 ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
67 smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
69 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
70 outb(byte | 0x80, 0xC00);
71 outb(intr_data[byte], 0xC01);
74 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
75 #define IO_LOCAL_INT(type, intr, apicid, pin) \
76 smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
78 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
80 /* PCI interrupts are level triggered, and are
81 * associated with a specific bus/device/function tuple.
83 #if CONFIG_GENERATE_ACPI_TABLES == 0
84 #define PCI_INT(bus, dev, fn, pin) \
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
87 #define PCI_INT(bus, dev, fn, pin)
90 PCI_INT(0x0, 0x14, 0x0, 0x10);
92 PCI_INT(0x0, 0x14, 0x2, 0x12);
93 PCI_INT(0x0, 0x14, 0x4, 0x11);
95 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
96 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
97 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
98 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
99 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
100 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
103 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
105 /* on board NIC & Slot PCIE. */
106 /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
107 /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
108 PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
109 /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
110 PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
111 /* configuration B doesnt need dev 5,6,7 */
113 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
114 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
115 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
117 PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
118 PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
122 PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
123 PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
124 PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
125 PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
128 PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
129 PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
130 PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
131 PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
134 PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
135 PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
136 PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
137 PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
139 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
140 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
141 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
142 /* There is no extension information... */
144 /* Compute the checksums */
146 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
147 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
148 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
149 mc, smp_next_mpe_entry(mc));
150 return smp_next_mpe_entry(mc);
153 unsigned long write_smp_table(unsigned long addr)
156 v = smp_write_floating_table(addr, 0);
157 return (unsigned long)smp_write_config_table(v);