2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
27 static void *smp_write_config_table(void *v)
29 static const char sig[4] = "PCMP";
30 static const char oem[8] = "COREBOOT";
31 static const char productid[12] = "ASUS P2B-DS ";
32 struct mp_config_table *mc;
34 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
35 memset(mc, 0, sizeof(*mc));
37 memcpy(mc->mpc_signature, sig, sizeof(sig));
38 mc->mpc_length = sizeof(*mc); /* initially just the header */
40 mc->mpc_checksum = 0; /* not yet computed */
41 memcpy(mc->mpc_oem, oem, sizeof(oem));
42 memcpy(mc->mpc_productid, productid, sizeof(productid));
45 mc->mpc_entry_count = 0; /* No entries yet... */
46 mc->mpc_lapic = LAPIC_ADDR;
51 smp_write_processors(mc);
53 /* Bus: Bus ID Type */
54 smp_write_bus(mc, 0, "PCI ");
55 smp_write_bus(mc, 1, "ISA ");
57 /* I/O APICs: APIC ID Version State Address */
58 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
63 dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
65 res = find_resource(dev, PCI_BASE_ADDRESS_0);
67 smp_write_ioapic(mc, 3, 0x20, res->base);
69 dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
71 res = find_resource(dev, PCI_BASE_ADDRESS_0);
73 smp_write_ioapic(mc, 4, 0x20, res->base);
75 dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
77 res = find_resource(dev, PCI_BASE_ADDRESS_0);
79 smp_write_ioapic(mc, 5, 0x20, res->base);
81 dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
83 res = find_resource(dev, PCI_BASE_ADDRESS_0);
85 smp_write_ioapic(mc, 8, 0x20, res->base);
89 mptable_add_isa_interrupts(mc, 0x1, 0x2, 0);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
92 0x0, 0x13, 0x2, 0x13);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
94 0x0, 0x18, 0x2, 0x13);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
96 0x0, 0x30, 0x2, 0x10);
98 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
99 smp_write_intsrc(mc, mp_ExtINT,
100 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0,
102 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
103 0x1, 0x0, MP_APIC_ALL, 0x1);
105 /* There is no extension information... */
107 /* Compute the checksums */
109 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
110 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
111 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
112 mc, smp_next_mpe_entry(mc));
113 return smp_next_mpe_entry(mc);
116 unsigned long write_smp_table(unsigned long addr)
119 v = smp_write_floating_table(addr);
120 return (unsigned long)smp_write_config_table(v);