2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## XIP_ROM_SIZE must be a power of 2.
22 default XIP_ROM_SIZE = 64 * 1024
23 include /config/nofailovercalculation.lb
27 if HAVE_MP_TABLE object mptable.o end
28 if HAVE_PIRQ_TABLE object irq_tables.o end
30 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
31 action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
33 makerule ./failover.inc
34 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
35 action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
38 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
39 depends "$(MAINBOARD)/auto.c ../romcc"
40 action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
43 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
44 depends "$(MAINBOARD)/auto.c ../romcc"
45 action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
47 mainboardinit cpu/x86/16bit/entry16.inc
48 mainboardinit cpu/x86/32bit/entry32.inc
49 ldscript /cpu/x86/16bit/entry16.lds
50 ldscript /cpu/x86/32bit/entry32.lds
52 mainboardinit cpu/x86/16bit/reset16.inc
53 ldscript /cpu/x86/16bit/reset16.lds
55 mainboardinit cpu/x86/32bit/reset32.inc
56 ldscript /cpu/x86/32bit/reset32.lds
58 mainboardinit arch/i386/lib/cpu_reset.inc
59 mainboardinit arch/i386/lib/id.inc
60 ldscript /arch/i386/lib/id.lds
62 ldscript /arch/i386/lib/failover.lds
63 mainboardinit ./failover.inc
65 mainboardinit cpu/x86/fpu/enable_fpu.inc
66 mainboardinit cpu/x86/mmx/enable_mmx.inc
67 mainboardinit ./auto.inc
68 mainboardinit cpu/x86/mmx/disable_mmx.inc
73 chip northbridge/intel/i440bx # Northbridge
74 device apic_cluster 0 on # APIC cluster
75 chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
76 device apic 0 on end # APIC
78 chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
79 device apic 1 on end # APIC
82 device pci_domain 0 on # PCI domain
83 device pci 0.0 on end # Host bridge
84 device pci 1.0 on end # PCI/AGP bridge
85 chip southbridge/intel/i82371eb # Southbridge
86 device pci 4.0 on # ISA bridge
87 chip superio/winbond/w83977tf # Super I/O
88 device pnp 3f0.0 on # Floppy
93 device pnp 3f0.1 on # Parallel port
97 device pnp 3f0.2 on # COM1
101 device pnp 3f0.3 on # COM2 / IR
105 device pnp 3f0.5 on # PS/2 keyboard / mouse
108 irq 0x70 = 1 # PS/2 keyboard interrupt
109 irq 0x72 = 12 # PS/2 mouse interrupt
111 device pnp 3f0.7 on # GPIO 1
113 device pnp 3f0.8 on # GPIO 2
115 device pnp 3f0.9 on # GPIO 3
117 device pnp 3f0.a on # ACPI
121 device pci 4.1 on end # IDE
122 device pci 4.2 on end # USB
123 device pci 4.3 on end # ACPI
124 register "ide0_enable" = "1"
125 register "ide1_enable" = "1"
126 register "ide_legacy_enable" = "1"
127 # Enable UDMA/33 for higher speed if your IDE device(s) support it.
128 register "ide0_drive0_udma33_enable" = "1"
129 register "ide0_drive1_udma33_enable" = "1"
130 register "ide1_drive0_udma33_enable" = "1"
131 register "ide1_drive1_udma33_enable" = "1"