1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_HAVE_OPTION_TABLE
7 uses CONFIG_USE_OPTION_TABLE
8 uses CONFIG_ROM_PAYLOAD
9 uses CONFIG_IRQ_SLOT_COUNT
11 uses CONFIG_MAINBOARD_VENDOR
12 uses CONFIG_MAINBOARD_PART_NUMBER
13 uses COREBOOT_EXTRA_VERSION
15 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_STACK_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_IMAGE_SIZE
21 uses CONFIG_ROM_SECTION_SIZE
22 uses CONFIG_ROM_SECTION_OFFSET
23 uses CONFIG_ROM_PAYLOAD_START
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
26 uses CONFIG_PAYLOAD_SIZE
29 uses CONFIG_XIP_ROM_SIZE
30 uses CONFIG_XIP_ROM_BASE
31 uses CONFIG_HAVE_MP_TABLE
32 uses CONFIG_CROSS_COMPILE
36 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
37 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
38 uses CONFIG_CONSOLE_SERIAL8250
39 uses CONFIG_TTYS0_BAUD
40 uses CONFIG_TTYS0_BASE
42 uses CONFIG_UDELAY_TSC
45 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
46 default CONFIG_ROM_SIZE = 512*1024
53 ## Build code for the fallback boot
55 default CONFIG_HAVE_FALLBACK_BOOT = 1
60 default CONFIG_HAVE_MP_TABLE = 0
63 ## Build code to reset the motherboard from coreboot
65 default CONFIG_HAVE_HARD_RESET = 0
68 ## Build code to export a programmable irq routing table
70 default CONFIG_HAVE_PIRQ_TABLE = 1
71 default CONFIG_IRQ_SLOT_COUNT = 11
74 ## Build code to export a CMOS option table
76 default CONFIG_HAVE_OPTION_TABLE = 0
79 default CONFIG_IDE = 1
82 ### coreboot layout values
85 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
86 default CONFIG_ROM_IMAGE_SIZE = 65536
87 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
90 ## Use a small 8K stack
92 default CONFIG_STACK_SIZE=0x2000
95 ## Use a small 16K heap
97 default CONFIG_HEAP_SIZE=0x4000
100 ## Only use the option table in a normal image
102 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
103 default CONFIG_USE_OPTION_TABLE = 0
105 default CONFIG_RAMBASE = 0x00004000
107 default CONFIG_ROM_PAYLOAD = 1
110 ## The default compiler
112 default CONFIG_CROSS_COMPILE=""
113 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
117 ## The Serial Console
120 # To Enable the Serial Console
121 default CONFIG_CONSOLE_SERIAL8250=1
123 ## Select the serial console baud rate
124 default CONFIG_TTYS0_BAUD=115200
125 #default CONFIG_TTYS0_BAUD=57600
126 #default CONFIG_TTYS0_BAUD=38400
127 #default CONFIG_TTYS0_BAUD=19200
128 #default CONFIG_TTYS0_BAUD=9600
129 #default CONFIG_TTYS0_BAUD=4800
130 #default CONFIG_TTYS0_BAUD=2400
131 #default CONFIG_TTYS0_BAUD=1200
133 # Select the serial console base port
134 default CONFIG_TTYS0_BASE=0x3f8
136 # Select the serial protocol
137 # This defaults to 8 data bits, 1 stop bit, and no parity
138 default CONFIG_TTYS0_LCS=0x3
141 ### Select the coreboot loglevel
143 ## EMERG 1 system is unusable
144 ## ALERT 2 action must be taken immediately
145 ## CRIT 3 critical conditions
146 ## ERR 4 error conditions
147 ## WARNING 5 warning conditions
148 ## NOTICE 6 normal but significant condition
149 ## INFO 7 informational
150 ## CONFIG_DEBUG 8 debug-level messages
151 ## SPEW 9 Way too many details
153 ## Request this level of debugging output
154 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
155 ## At a maximum only compile in this level of debugging
156 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
158 default CONFIG_UDELAY_TSC=1