1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_HAVE_OPTION_TABLE
7 uses CONFIG_USE_OPTION_TABLE
8 uses CONFIG_ROM_PAYLOAD
9 uses CONFIG_IRQ_SLOT_COUNT
11 uses CONFIG_MAINBOARD_VENDOR
12 uses CONFIG_MAINBOARD_PART_NUMBER
13 uses COREBOOT_EXTRA_VERSION
15 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_STACK_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_IMAGE_SIZE
21 uses CONFIG_ROM_SECTION_SIZE
22 uses CONFIG_ROM_SECTION_OFFSET
23 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
24 uses CONFIG_PRECOMPRESSED_PAYLOAD
27 uses CONFIG_XIP_ROM_SIZE
28 uses CONFIG_XIP_ROM_BASE
29 uses CONFIG_GENERATE_MP_TABLE
30 uses CONFIG_CROSS_COMPILE
34 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
35 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
36 uses CONFIG_CONSOLE_SERIAL8250
37 uses CONFIG_TTYS0_BAUD
38 uses CONFIG_TTYS0_BASE
40 uses CONFIG_UDELAY_TSC
43 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
44 default CONFIG_ROM_SIZE = 512*1024
51 ## Build code for the fallback boot
53 default CONFIG_HAVE_FALLBACK_BOOT = 1
58 default CONFIG_GENERATE_MP_TABLE = 0
61 ## Build code to reset the motherboard from coreboot
63 default CONFIG_HAVE_HARD_RESET = 0
66 ## Build code to export a programmable irq routing table
68 default CONFIG_GENERATE_PIRQ_TABLE = 1
69 default CONFIG_IRQ_SLOT_COUNT = 11
72 ## Build code to export a CMOS option table
74 default CONFIG_HAVE_OPTION_TABLE = 0
77 default CONFIG_IDE = 1
80 ### coreboot layout values
83 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
84 default CONFIG_ROM_IMAGE_SIZE = 65536
85 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
88 ## Use a small 8K stack
90 default CONFIG_STACK_SIZE=0x2000
93 ## Use a small 16K heap
95 default CONFIG_HEAP_SIZE=0x4000
98 ## Only use the option table in a normal image
100 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
101 default CONFIG_USE_OPTION_TABLE = 0
103 default CONFIG_RAMBASE = 0x00004000
105 default CONFIG_ROM_PAYLOAD = 1
108 ## The default compiler
110 default CONFIG_CROSS_COMPILE=""
111 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
115 ## The Serial Console
118 # To Enable the Serial Console
119 default CONFIG_CONSOLE_SERIAL8250=1
121 ## Select the serial console baud rate
122 default CONFIG_TTYS0_BAUD=115200
123 #default CONFIG_TTYS0_BAUD=57600
124 #default CONFIG_TTYS0_BAUD=38400
125 #default CONFIG_TTYS0_BAUD=19200
126 #default CONFIG_TTYS0_BAUD=9600
127 #default CONFIG_TTYS0_BAUD=4800
128 #default CONFIG_TTYS0_BAUD=2400
129 #default CONFIG_TTYS0_BAUD=1200
131 # Select the serial console base port
132 default CONFIG_TTYS0_BASE=0x3f8
134 # Select the serial protocol
135 # This defaults to 8 data bits, 1 stop bit, and no parity
136 default CONFIG_TTYS0_LCS=0x3
139 ### Select the coreboot loglevel
141 ## EMERG 1 system is unusable
142 ## ALERT 2 action must be taken immediately
143 ## CRIT 3 critical conditions
144 ## ERR 4 error conditions
145 ## WARNING 5 warning conditions
146 ## NOTICE 6 normal but significant condition
147 ## INFO 7 informational
148 ## CONFIG_DEBUG 8 debug-level messages
149 ## SPEW 9 Way too many details
151 ## Request this level of debugging output
152 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
153 ## At a maximum only compile in this level of debugging
154 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
156 default CONFIG_UDELAY_TSC=1