src/mainboard/asus/mew-vm/Config.lb

   1 include /config/nofailovercalculation.lb
   2
   3 ##
   4 ## Set all of the defaults for an x86 architecture
   5 ##
   6
   7 arch i386 end
   8
   9 ##
  10 ## Build the objects we have code for in this directory.
  11 ##
  12
  13 driver mainboard.o
  14
  15 if HAVE_PIRQ_TABLE object irq_tables.o end
  16 #object reset.o
  17
  18 ##
  19 ## Romcc output
  20 ##
  21 makerule ./failover.E
  22         depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  23         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  24 end
  25
  26 makerule ./failover.inc
  27         depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  28         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  29 end
  30
  31 makerule ./auto.E
  32         depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  33         action  "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  34 end
  35 makerule ./auto.inc
  36         depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  37         action  "../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  38 end
  39
  40 ##
  41 ## Build our 16 bit and 32 bit coreboot entry code
  42 ##
  43 mainboardinit cpu/x86/16bit/entry16.inc
  44 mainboardinit cpu/x86/32bit/entry32.inc
  45 ldscript /cpu/x86/16bit/entry16.lds
  46 ldscript /cpu/x86/32bit/entry32.lds
  47
  48 ##
  49 ## Build our reset vector (This is where coreboot is entered)
  50 ##
  51 if USE_FALLBACK_IMAGE
  52         mainboardinit cpu/x86/16bit/reset16.inc
  53         ldscript /cpu/x86/16bit/reset16.lds
  54 else
  55         mainboardinit cpu/x86/32bit/reset32.inc
  56         ldscript /cpu/x86/32bit/reset32.lds
  57 end
  58
  59 ### Should this be in the northbridge code?
  60 mainboardinit arch/i386/lib/cpu_reset.inc
  61
  62 ##
  63 ## Include an id string (For safe flashing)
  64 ##
  65 mainboardinit arch/i386/lib/id.inc
  66 ldscript /arch/i386/lib/id.lds
  67
  68 ###
  69 ### This is the early phase of coreboot startup
  70 ### Things are delicate and we test to see if we should
  71 ### failover to another image.
  72 ###
  73 if USE_FALLBACK_IMAGE
  74         ldscript /arch/i386/lib/failover.lds
  75         mainboardinit ./failover.inc
  76 end
  77
  78 ###
  79 ### O.k. We aren't just an intermediary anymore!
  80 ###
  81
  82 ##
  83 ## Setup RAM
  84 ##
  85 mainboardinit cpu/x86/fpu/enable_fpu.inc
  86 mainboardinit cpu/x86/mmx/enable_mmx.inc
  87 mainboardinit ./auto.inc
  88 mainboardinit cpu/x86/mmx/disable_mmx.inc
  89
  90 ##
  91 ## Include the secondary Configuration files
  92 ##
  93 dir /pc80
  94 config chip.h
  95
  96 chip northbridge/intel/i82810
  97         device pci_domain 0 on
  98                 device pci 0.0 on end # Host bridge
  99                 device pci 1.0 on # Onboard Video
 100                         #chip drivers/pci/onboard
 101                         #       device pci 1.0 on end
 102                         #       register "rom_address" = "0xfff80000"
 103                         #end
 104                 end
 105                 chip southbridge/intel/i82801xx # Southbridge
 106                         device pci 1e.0 on # PCI Bridge
 107                                 #chip drivers/pci/onboard
 108                                 #       device pci 1.0 on end
 109                                 #       register "rom_address" = "0xfff80000"
 110                                 #end
 111                         end
 112                         device pci 1f.0 on  # ISA/LPC? Bridge
 113                                 chip superio/smsc/lpc47b272
 114                                         device pnp 2e.0 off # Floppy
 115                                                 io 0x60 = 0x3f0
 116                                                 irq 0x70 = 6
 117                                                 drq 0x74 = 2
 118                                         end
 119                                         device pnp 2e.3 off # Parallel Port
 120                                                 io 0x60 = 0x378
 121                                                 irq 0x70 = 7
 122                                         end
 123                                         device pnp 2e.4 on # Com1
 124                                                 io 0x60 = 0x3f8
 125                                                 irq 0x70 = 4
 126                                         end
 127                                         device pnp 2e.5 off # Com2
 128                                                 io 0x60 = 0x2f8
 129                                                 irq 0x70 = 3
 130                                         end
 131                                         device pnp 2e.7 on # Keyboard
 132                                                 io 0x60 = 0x60
 133                                                 io 0x62 = 0x64
 134                                                 irq 0x70 = 1 # Keyboard interrupt
 135                                                 irq 0x72 = 12 # Mouse interrupt
 136                                         end
 137                                         device pnp 2e.a off end # ACPI
 138                                 end
 139                         end
 140                         device pci 1f.1 on end # IDE
 141                         device pci 1f.2 on end # USB
 142                         device pci 1f.3 on end # SMBus
 143                         device pci 1f.5 off end # AC'97, no header on MEW-VM
 144                         device pci 1f.6 off end # AC'97 Modem (MC'97)
 145                 end
 146         end
 147         chip cpu/intel/socket_PGA370
 148         end
 149 end
 150