src/mainboard/asus/mew-vm/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  18 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 ##
  51 ## Romcc output
  52 ##
  53 makerule ./failover.E
  54         depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  55         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  56 end
  57
  58 makerule ./failover.inc
  59         depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  60         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  61 end
  62
  63 makerule ./auto.E
  64         depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  65         action  "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  66 end
  67 makerule ./auto.inc
  68         depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  69         action  "../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  70 end
  71
  72 ##
  73 ## Build our 16 bit and 32 bit coreboot entry code
  74 ##
  75 mainboardinit cpu/x86/16bit/entry16.inc
  76 mainboardinit cpu/x86/32bit/entry32.inc
  77 ldscript /cpu/x86/16bit/entry16.lds
  78 ldscript /cpu/x86/32bit/entry32.lds
  79
  80 ##
  81 ## Build our reset vector (This is where coreboot is entered)
  82 ##
  83 if USE_FALLBACK_IMAGE
  84         mainboardinit cpu/x86/16bit/reset16.inc
  85         ldscript /cpu/x86/16bit/reset16.lds
  86 else
  87         mainboardinit cpu/x86/32bit/reset32.inc
  88         ldscript /cpu/x86/32bit/reset32.lds
  89 end
  90
  91 ### Should this be in the northbridge code?
  92 mainboardinit arch/i386/lib/cpu_reset.inc
  93
  94 ##
  95 ## Include an id string (For safe flashing)
  96 ##
  97 mainboardinit arch/i386/lib/id.inc
  98 ldscript /arch/i386/lib/id.lds
  99
 100 ###
 101 ### This is the early phase of coreboot startup
 102 ### Things are delicate and we test to see if we should
 103 ### failover to another image.
 104 ###
 105 if USE_FALLBACK_IMAGE
 106         ldscript /arch/i386/lib/failover.lds
 107         mainboardinit ./failover.inc
 108 end
 109
 110 ###
 111 ### O.k. We aren't just an intermediary anymore!
 112 ###
 113
 114 ##
 115 ## Setup RAM
 116 ##
 117 mainboardinit cpu/x86/fpu/enable_fpu.inc
 118 mainboardinit cpu/x86/mmx/enable_mmx.inc
 119 mainboardinit ./auto.inc
 120 mainboardinit cpu/x86/mmx/disable_mmx.inc
 121
 122 ##
 123 ## Include the secondary Configuration files
 124 ##
 125 dir /pc80
 126 config chip.h
 127
 128 chip northbridge/intel/i82810
 129         device pci_domain 0 on
 130                 device pci 0.0 on end # Host bridge
 131                 device pci 1.0 on # Onboard Video
 132                         #chip drivers/pci/onboard
 133                         #       device pci 1.0 on end
 134                         #       register "rom_address" = "0xfff80000"
 135                         #end
 136                 end
 137                 chip southbridge/intel/i82801xx # Southbridge
 138                         device pci 1e.0 on # PCI Bridge
 139                                 #chip drivers/pci/onboard
 140                                 #       device pci 1.0 on end
 141                                 #       register "rom_address" = "0xfff80000"
 142                                 #end
 143                         end
 144                         device pci 1f.0 on  # ISA/LPC? Bridge
 145                                 chip superio/smsc/lpc47b272
 146                                         device pnp 2e.0 off # Floppy
 147                                                 io 0x60 = 0x3f0
 148                                                 irq 0x70 = 6
 149                                                 drq 0x74 = 2
 150                                         end
 151                                         device pnp 2e.3 off # Parallel Port
 152                                                 io 0x60 = 0x378
 153                                                 irq 0x70 = 7
 154                                         end
 155                                         device pnp 2e.4 on # Com1
 156                                                 io 0x60 = 0x3f8
 157                                                 irq 0x70 = 4
 158                                         end
 159                                         device pnp 2e.5 off # Com2
 160                                                 io 0x60 = 0x2f8
 161                                                 irq 0x70 = 3
 162                                         end
 163                                         device pnp 2e.7 on # Keyboard
 164                                                 io 0x60 = 0x60
 165                                                 io 0x62 = 0x64
 166                                                 irq 0x70 = 1 # Keyboard interrupt
 167                                                 irq 0x72 = 12 # Mouse interrupt
 168                                         end
 169                                         device pnp 2e.a off end # ACPI
 170                                 end
 171                         end
 172                         device pci 1f.1 on end # IDE
 173                         device pci 1f.2 on end # USB
 174                         device pci 1f.3 on end # SMBus
 175                         device pci 1f.5 off end # AC'97, no header on MEW-VM
 176                         device pci 1f.6 off end # AC'97 Modem (MC'97)
 177                 end
 178         end
 179         chip cpu/intel/socket_PGA370
 180         end
 181 end
 182