src/mainboard/asus/mew-vm/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16
  17 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  18
  19 ##
  20 ## Romcc output
  21 ##
  22 makerule ./failover.E
  23         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  24         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  25 end
  26
  27 makerule ./failover.inc
  28         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  29         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  30 end
  31
  32 makerule ./auto.E
  33         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  34         action  "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  35 end
  36 makerule ./auto.inc
  37         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  38         action  "../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  39 end
  40
  41 ##
  42 ## Build our 16 bit and 32 bit coreboot entry code
  43 ##
  44 mainboardinit cpu/x86/16bit/entry16.inc
  45 mainboardinit cpu/x86/32bit/entry32.inc
  46 ldscript /cpu/x86/16bit/entry16.lds
  47 ldscript /cpu/x86/32bit/entry32.lds
  48
  49 ##
  50 ## Build our reset vector (This is where coreboot is entered)
  51 ##
  52 if CONFIG_USE_FALLBACK_IMAGE
  53         mainboardinit cpu/x86/16bit/reset16.inc
  54         ldscript /cpu/x86/16bit/reset16.lds
  55 else
  56         mainboardinit cpu/x86/32bit/reset32.inc
  57         ldscript /cpu/x86/32bit/reset32.lds
  58 end
  59
  60 ### Should this be in the northbridge code?
  61 mainboardinit arch/i386/lib/cpu_reset.inc
  62
  63 ##
  64 ## Include an id string (For safe flashing)
  65 ##
  66 mainboardinit arch/i386/lib/id.inc
  67 ldscript /arch/i386/lib/id.lds
  68
  69 ###
  70 ### This is the early phase of coreboot startup
  71 ### Things are delicate and we test to see if we should
  72 ### failover to another image.
  73 ###
  74 if CONFIG_USE_FALLBACK_IMAGE
  75         ldscript /arch/i386/lib/failover.lds
  76         mainboardinit ./failover.inc
  77 end
  78
  79 ###
  80 ### O.k. We aren't just an intermediary anymore!
  81 ###
  82
  83 ##
  84 ## Setup RAM
  85 ##
  86 mainboardinit cpu/x86/fpu_enable.inc
  87 mainboardinit ./auto.inc
  88 mainboardinit cpu/x86/mmx_disable.inc
  89
  90 ##
  91 ## Include the secondary Configuration files
  92 ##
  93 dir /pc80
  94 config chip.h
  95
  96 chip northbridge/intel/i82810
  97         device pci_domain 0 on
  98                 device pci 0.0 on end # Host bridge
  99                 device pci 1.0 on # Onboard Video
 100                         #chip drivers/pci/onboard
 101                         #       device pci 1.0 on end
 102                         #       register "rom_address" = "0xfff80000"
 103                         #end
 104                 end
 105                 chip southbridge/intel/i82801xx # Southbridge
 106                         register "ide0_enable" = "1"
 107                         register "ide1_enable" = "1"
 108
 109                         device pci 1e.0 on # PCI Bridge
 110                                 #chip drivers/pci/onboard
 111                                 #       device pci 1.0 on end
 112                                 #       register "rom_address" = "0xfff80000"
 113                                 #end
 114                         end
 115                         device pci 1f.0 on  # ISA/LPC? Bridge
 116                                 chip superio/smsc/lpc47b272
 117                                         device pnp 2e.0 off # Floppy
 118                                                 io 0x60 = 0x3f0
 119                                                 irq 0x70 = 6
 120                                                 drq 0x74 = 2
 121                                         end
 122                                         device pnp 2e.3 off # Parallel Port
 123                                                 io 0x60 = 0x378
 124                                                 irq 0x70 = 7
 125                                         end
 126                                         device pnp 2e.4 on # Com1
 127                                                 io 0x60 = 0x3f8
 128                                                 irq 0x70 = 4
 129                                         end
 130                                         device pnp 2e.5 off # Com2
 131                                                 io 0x60 = 0x2f8
 132                                                 irq 0x70 = 3
 133                                         end
 134                                         device pnp 2e.7 on # Keyboard
 135                                                 io 0x60 = 0x60
 136                                                 io 0x62 = 0x64
 137                                                 irq 0x70 = 1 # Keyboard interrupt
 138                                                 irq 0x72 = 12 # Mouse interrupt
 139                                         end
 140                                         device pnp 2e.a off end # ACPI
 141                                 end
 142                         end
 143                         device pci 1f.1 on end # IDE
 144                         device pci 1f.2 on end # USB
 145                         device pci 1f.3 on end # SMBus
 146                         device pci 1f.5 off end # AC'97, no header on MEW-VM
 147                         device pci 1f.6 off end # AC'97 Modem (MC'97)
 148                 end
 149         end
 150         chip cpu/intel/socket_PGA370
 151         end
 152 end
 153