2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 //#define SYSTEM_TYPE 0 /* SERVER */
21 #define SYSTEM_TYPE 1 /* DESKTOP */
22 //#define SYSTEM_TYPE 2 /* MOBILE */
24 //used by incoherent_ht
25 #define FAM10_SCAN_PCI_BUS 0
26 #define FAM10_ALLOCATE_IO_RANGE 0
31 #include <device/pci_def.h>
32 #include <device/pci_ids.h>
34 #include <device/pnp_def.h>
35 #include <arch/romcc_io.h>
36 #include <cpu/x86/lapic.h>
37 #include <console/console.h>
38 #include <cpu/amd/model_10xxx_rev.h>
39 #include "northbridge/amd/amdfam10/raminit.h"
40 #include "northbridge/amd/amdfam10/amdfam10.h"
41 #include "cpu/x86/lapic/boot_cpu.c"
42 #include "northbridge/amd/amdfam10/reset_test.c"
43 #include <console/loglevel.h>
44 #include "cpu/x86/bist.h"
45 #include "superio/ite/it8721f/early_serial.c"
46 #include "cpu/x86/mtrr/earlymtrr.c"
47 #include <cpu/amd/mtrr.h>
48 #include "northbridge/amd/amdfam10/setup_resource_map.c"
50 #include <southbridge/amd/cimx/sb900/SbEarly.h>
51 #include <southbridge/amd/cimx/sb900/SbPlatform.h> /* SB OEM constants */
52 #include <southbridge/amd/cimx/sb900/smbus.h>
53 #include "northbridge/amd/amdfam10/debug.c"
55 static void activate_spd_rom(const struct mem_controller *ctrl)
59 static int spd_read_byte(u32 device, u32 address)
61 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
64 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
65 #include "northbridge/amd/amdfam10/pci.c"
66 #include "resourcemap.c"
67 #include "cpu/amd/quadcore/quadcore.c"
68 #include "cpu/amd/car/post_cache_as_ram.c"
69 #include "cpu/amd/microcode/microcode.c"
70 #if CONFIG_UPDATE_CPU_MICROCODE
71 #include "cpu/amd/model_10xxx/update_microcode.c"
73 #include "cpu/amd/model_10xxx/init_cpus.c"
74 #include "northbridge/amd/amdfam10/early_ht.c"
85 #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
86 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
88 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
89 static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
90 u32 bsp_apicid = 0, val;
93 if (!cpu_init_detectedx && boot_cpu()) {
94 /* Nothing special needs to be done to find bus 0 */
95 /* Allow the HT devices to be found */
96 /* mov bsp to bus 0xff when > 8 nodes */
97 set_bsp_node_CHtExtNodeCfgEn();
100 //enable port80 decoding and southbridge poweron init
107 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
108 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
113 it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
116 printk(BIOS_DEBUG, "\n");
119 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
121 /* Halt if there was a built in self test failure */
122 report_bist_failure(bist);
126 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
127 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
128 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
129 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
131 /* Setup sysinfo defaults */
132 set_sysinfo_in_ram(0);
134 #if CONFIG_UPDATE_CPU_MICROCODE
135 update_microcode(val);
142 amd_ht_init(sysinfo);
145 /* Setup nodes PCI space and start core 0 AP init. */
146 finalize_node_setup(sysinfo);
148 /* Setup any mainboard PCI settings etc. */
149 setup_mb_resource_map();
152 /* wait for all the APs core0 started by finalize_node_setup. */
153 /* FIXME: A bunch of cores are going to start output to serial at once.
154 It would be nice to fixup prink spinlocks for ROM XIP mode.
155 I think it could be done by putting the spinlock flag in the cache
156 of the BSP located right after sysinfo.
158 wait_all_core0_started();
160 #if CONFIG_LOGICAL_CPUS==1
161 /* Core0 on each node is configured. Now setup any additional cores. */
162 printk(BIOS_DEBUG, "start_other_cores()\n");
165 wait_all_other_cores_started(bsp_apicid);
170 sr56x0_rd890_disable_pcie_bridge();
173 #if CONFIG_SET_FIDVID == 1
174 msr = rdmsr(0xc0010071);
175 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
178 if (!warm_reset_detect(0)) { // BSP is node 0
179 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
181 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
186 /* show final fid and vid */
187 msr=rdmsr(0xc0010071);
188 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
193 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
194 if (!warm_reset_detect(0)) {
195 print_info("...WARM RESET...\n\n\n");
197 die("After soft_reset_x - shouldn't see this message!!!\n");
202 /* It's the time to set ctrl in sysinfo now; */
203 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
204 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
208 // die("Die Before MCT init.");
210 printk(BIOS_DEBUG, "raminit_amdmct()\n");
211 raminit_amdmct(sysinfo);
215 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
216 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
217 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
218 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
221 // ram_check(0x00200000, 0x00200000 + (640 * 1024));
222 // ram_check(0x40200000, 0x40200000 + (640 * 1024));
224 // die("After MCT init before CAR disabled.");
227 rs780_before_pci_init();
231 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
232 post_code(0x43); // Should never see this post code.
236 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
238 * This routine is called every time a non-coherent chain is processed.
239 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
240 * swap list. The first part of the list controls the BUID assignment and the
241 * second part of the list provides the device to device linking. Device orientation
242 * can be detected automatically, or explicitly. See documentation for more details.
244 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
245 * based on each device's unit count.
248 * @param[in] u8 node = The node on which this chain is located
249 * @param[in] u8 link = The link on the host for this chain
250 * @param[out] u8** list = supply a pointer to a list
251 * @param[out] BOOL result = true to use a manual list
252 * false to initialize the link automatically
254 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
256 static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
257 /* If the BUID was adjusted in early_ht we need to do the manual override */
258 if ((node == 0) && (link == 0)) { /* BSP SB link */