2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <cpu/x86/msr.h>
25 #include <cpu/amd/mtrr.h>
26 #include <device/pci_def.h>
27 #include "southbridge/amd/sb700/sb700.h"
28 #include "southbridge/amd/sb700/smbus.h"
31 #define ADT7461_ADDRESS 0x4C
32 #define ARA_ADDRESS 0x0C /* Alert Response Address */
34 #define ADT7461_read_byte(address) \
35 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
36 #define ARA_read_byte(address) \
37 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
38 #define ADT7461_write_byte(address, val) \
39 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
41 uint64_t uma_memory_base, uma_memory_size;
43 void set_pcie_dereset(void);
44 void set_pcie_reset(void);
45 u8 is_dev3_present(void);
47 void set_pcie_dereset()
52 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
53 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
54 byte = pm_ioread(0x8d);
55 byte &= ~((1 << 1) | (1 << 2));
56 pm_iowrite(0x8d, byte);
58 /* set the GPM8 and GPM9 output enable and the value to 1 */
59 byte = pm_ioread(0x94);
60 byte &= ~((1 << 2) | (1 << 3));
61 byte |= ((1 << 0) | (1 << 1));
62 pm_iowrite(0x94, byte);
64 /* set the GPIO65 output enable and the value is 1 */
65 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
66 word = pci_read_config16(sm_dev, 0x7e);
69 pci_write_config16(sm_dev, 0x7e, word);
78 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
79 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
80 byte = pm_ioread(0x8d);
81 byte &= ~((1 << 1) | (1 << 2));
82 pm_iowrite(0x8d, byte);
84 /* set the GPM8 and GPM9 output enable and the value to 0 */
85 byte = pm_ioread(0x94);
86 byte &= ~((1 << 2) | (1 << 3));
87 byte &= ~((1 << 0) | (1 << 1));
88 pm_iowrite(0x94, byte);
90 /* set the GPIO65 output enable and the value is 0 */
91 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
92 word = pci_read_config16(sm_dev, 0x7e);
95 pci_write_config16(sm_dev, 0x7e, word);
99 * justify the dev3 is exist or not
100 * NOTE: This just copied from AMD Tilapia code.
101 * It is completly unknown it it will work at all for ASUS M4A785-M.
103 u8 is_dev3_present(void)
108 /* access the smbus extended register */
109 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
111 /* put the GPIO68 output to tristate */
112 word = pci_read_config16(sm_dev, 0x7e);
114 pci_write_config16(sm_dev, 0x7e,word);
116 /* read the GPIO68 input status */
117 word = pci_read_config16(sm_dev, 0x7e);
119 if(word & (1 << 10)){
131 static void set_thermal_config(void)
138 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
139 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
140 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
141 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
143 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
144 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
146 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
147 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
148 printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
150 /* sb700 settings for thermal config */
151 /* set SB700 GPIO 64 to GPIO with pull-up */
152 byte = pm2_ioread(0x42);
154 pm2_iowrite(0x42, byte);
156 /* set GPIO 64 to input */
157 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
158 word = pci_read_config16(sm_dev, 0x56);
160 pci_write_config16(sm_dev, 0x56, word);
162 /* set GPIO 64 internal pull-up */
163 byte = pm2_ioread(0xf0);
165 pm2_iowrite(0xf0, byte);
167 /* set Talert to be active low */
168 byte = pm_ioread(0x67);
170 pm_iowrite(0x67, byte);
172 /* set Talert to generate ACPI event */
173 byte = pm_ioread(0x3c);
175 pm_iowrite(0x3c, byte);
178 /* byte = pm_ioread(0x68);
180 * pm_iowrite(0x68, byte);
182 * byte = pm_ioread(0x55);
184 * pm_iowrite(0x55, byte);
186 * byte = pm_ioread(0x67);
187 * byte &= ~( 1 << 6);
188 * pm_iowrite(0x67, byte);
192 /*************************************************
193 * enable the dedicated function in this board.
194 * This function called early than rs780_enable.
195 *************************************************/
196 static void m4a785m_enable(device_t dev)
198 printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
200 #if (CONFIG_GFXUMA == 1)
203 /* TOP_MEM: the top of DRAM below 4G */
204 msr = rdmsr(TOP_MEM);
206 "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
207 __func__, msr.lo, msr.hi);
209 /* TOP_MEM2: the top of DRAM above 4G */
210 msr2 = rdmsr(TOP_MEM2);
212 "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
213 __func__, msr2.lo, msr2.hi);
216 case 0x10000000: /* 256M system memory */
217 uma_memory_size = 0x4000000; /* 64M recommended UMA */
220 case 0x20000000: /* 512M system memory */
221 uma_memory_size = 0x8000000; /* 128M recommended UMA */
224 default: /* 1GB and above system memory */
225 uma_memory_size = 0x10000000; /* 256M recommended UMA */
229 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
230 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
231 __func__, uma_memory_size, uma_memory_base);
235 uma_memory_size = 0x8000000; /* 128M recommended UMA */
236 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
240 /* get_ide_dma66(); */
241 set_thermal_config();
244 struct chip_operations mainboard_ops = {
245 #ifdef CONFIG_BOARD_ASUS_M4A785TM
246 CHIP_NAME("ASUS M4A785T-M Mainboard")
248 CHIP_NAME("ASUS M4A785-M Mainboard")
250 .enable_dev = m4a785m_enable,